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how to ignore the warning? #1073
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Original Redmine Comment Generally two ways to disable warning. You can add some comments in the verilog source where the warning is reported, then the particular warning will be ignored.
Another way is to disable all STMTDLY warning by adding
option when you invoke Verilator. |
Original Redmine Comment %Warning-STMTDLY: our.v:20: Unsupported: Ignoring delay on this delayed statement. The problem is solved, but I found that the delay(such as "#10") has been optimized and ignored. It didn't work. |
Original Redmine Comment I am sorry. I have saw that Verilator simulates synthesizable verilog code in documentation. But there still is a foolish question in my mind--how to simulate(provide input)? We write testbench by verilogHDL when using ModelSim, does it need use SystemC/C++ to create the testbench if we use Verilator? Then the testbench will be very complex in order to test all the situations, but the authority said it just need write a touch of C code and Makefiles after synthesizable verilog is migrated to C++ or SystemC. |
Original Redmine Comment No change needed. See also the errors and warnings section of the manual, to which I made a tweak in git to mention config files. |
Author Name: nan wu
Original Redmine Issue: 1073 from https://www.veripool.org
Original Date: 2016-07-12
I am a new user. There will be warnings and error When there is a delay(such as '#10') in the verilog module. It shows" Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. "
So I added "lint_off -msg STMTDLY" in file named t_vlt_warn.vlt. But it didn't work.
Please help me !
Thanks very much!
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