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Question: alignment(input wire autoinst) #1184

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veripoolbot opened this issue Jul 31, 2017 · 5 comments
Closed

Question: alignment(input wire autoinst) #1184

veripoolbot opened this issue Jul 31, 2017 · 5 comments
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@veripoolbot
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Author Name: 波 王
Original Redmine Message: 2308 from https://www.veripool.org


now

module peak_detect
  (
    input          clk,
    input          rst,
    input [15:00]  mag_in,
    input [15:00]  threshold,

    output         peak_detect_end,
    output [04:00] peak_delay
    );

    wire           new_max;                // From max_detect of max_detect.v
    wire           reset_search;           // From max_detect of max_detect.v

    max_detect max_detect
      (/*AUTOINST*/
       // Outputs
       .reset_search                     ( reset_search),
       .new_max                          ( new_max),
       // Inputs
       .clk                              ( clk),
       .rst                              ( rst),
       .mag_in                           ( mag_in[15:00]),
       .threshold                        ( threshold[15:00]));


After

module peak_detect
  (
    input           clk            ,
    input           rst            ,
    input  [15:00]  mag_in         ,
    input  [15:00]  threshold      ,
                                    
    output         peak_detect_end ,
    output [04:00] peak_delay
    );

    wire           new_max         ;           // From max_detect of max_detect.v
    wire           reset_search    ;           // From max_detect of max_detect.v

    max_detect max_detect
      (/*AUTOINST*/
       // Outputs
       .reset_search                     ( reset_search     ),
       .new_max                          ( new_max          ),
       // Inputs                                             
       .clk                              ( clk              ),
       .rst                              ( rst              ),
       .mag_in                           ( mag_in[15:00]    ),
       .threshold                        ( threshold[15:00] ));
    
endmodule // peak_detect

How can i modify lisp ?

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-08-07T12:30:52Z


There is no setting at present to change the indentation style of AUTO generated text. This would be very complicated and slow as it would need to make multiple passes to determine the proper spacing. I suggest living with what it does now. Otherwise, if you want to support this you will need to edit the lisp sources yourself, sorry.

@veripoolbot
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Original Redmine Comment
Author Name: Jie Xiao
Original Date: 2018-04-18T16:13:00Z


I think it is not complicated, say for each line,you suppose jump 40 blank, if the signal name length (N) is less than 40, you add (40-N) blank, it will align

@veripoolbot
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Original Redmine Comment
Author Name: Jie Xiao
Original Date: 2018-04-18T22:04:37Z


  ( insert " " (verilog-sig-memory sig)))
     (setq slen (- 40 (length (verilog-sig-name (car sigs)))))
    (while (> slen 0)
    (insert " ")
    (setq slen (- slen 1))
  )

@szkarn
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szkarn commented Nov 20, 2023

Original Redmine Comment Author Name: Jie Xiao Original Date: 2018-04-18T22:04:37Z

  ( insert " " (verilog-sig-memory sig)))
     (setq slen (- 40 (length (verilog-sig-name (car sigs)))))
    (while (> slen 0)
    (insert " ")
    (setq slen (- slen 1))
  )

I am interested to this too. I try to write this into the verilog-mode.el, but it does not work. Could you give more infor?

@wsnyder
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wsnyder commented Nov 20, 2023

Generally better not to comment on closed 5 year old issues. But: 1. The short answer is if you want to use code someone posted, it's on you to debug it ;) 2. The longer answer is already above "There is no setting at present to change the indentation style of AUTO generated text. This would be very complicated and slow as it would need to make multiple passes to determine the proper spacing. I suggest living with what it does now. Otherwise, if you want to support this you will need to edit the lisp sources yourself, sorry.

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