parameter W = 1;

  output [W-1:0]f;
  input [W-1:0]a, b;

  supply0 gnd;
  supply1 vcc;

  generate
     genvar i;
     for (i = 0; i < W; i = i + 1) begin
       wire w;
       pmos (f[i], w, a[i]);
       pmos (w, vcc, b[i]);
       nmos (f[i], gnd, a[i]);
       nmos (f[i], gnd, b[i]);
     end
  endgenerate
endmodule  // fnor2

module test(f, a, b);
  output [1:0]f;
  input [1:0]a, b;

  fnor2 #(2) n(f, a, b);
endmodule

$ verilator --version
Verilator 3.916 2017-11-25 rev verilator_3_914-65-g0478dbd
$ verilator -I --cc bug.v --trace --top-module test -Mdir ../obj -CFLAGS "-O2 -std=c++11 -fPIC"
%Error: bug.v:13: Duplicate declaration of signal: test.n.w__en
%Error: bug.v:13: ... Location of original declaration
%Error: Exiting due to 1 error(s)
%Error: Command Failed /usr/bin/verilator_bin -I --cc bug.v --trace --top-module test -Mdir ../obj -CFLAGS '-O2 -std=c++11 -fPIC'