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Question: How can I use AUTOs to add the input/output attribution info. like "i_/o_" or "_i/_o" to the wires? #1417

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veripoolbot opened this issue May 13, 2019 · 3 comments
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Question: How can I use AUTOs to add the input/output attribution info. like "i_/o_" or "_i/_o" to the wires? #1417

veripoolbot opened this issue May 13, 2019 · 3 comments
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Author Name: Chen Jay
Original Redmine Message: 2964 from https://www.veripool.org

I want to use AUTOs to add the input/output attribution info. like "i_/o_" or "_i/_o" to the connection wires, like:

inst inst (/* AUTOINST*
         //Outputs
         .lower_out (o_lower_out),
         //Inputs
         . lower_inb(i_lower_inb),
         . lower_ina (i_lower_ina));

or:

inst inst (/* AUTOINST*
         //Outputs
         .lower_out (lower_out_o),
         //Inputs
         . lower_inb(lower_inb_i),
         . lower_ina (lower_ina_i));

but do not know how to realize it, could you help on this.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-05-13T12:27:25Z

Use something like this:

  /* inst AUTO_TEMPLATE (
    .\(.*\) (@"(if (equal vl-dir \\"output\\") \\"o_\\" \\"i_\\")"\1),
    );
    */

That is for every signal, look at direction and if an output add o_ otherwise i_, followed by original signal name.

@veripoolbot
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Original Redmine Comment
Author Name: Chen Jay
Original Date: 2019-05-14T00:34:01Z

Thanks for your kindly help！！！！！！！！

Best Regards，
Chen Jay

@veripoolbot
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Original Redmine Comment
Author Name: Chen Jay
Original Date: 2019-05-15T01:19:01Z

Just for memo：

Add input/output/inout info. like "i_/o_/io_" to the wires:

.\(.*\) (@"(if (equal vl-dir \\"output\\") \\"o_\\" (if (equal vl-dir \\"input\\") \\"i_\\" \\"io_\\"))"\1[]),

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