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Verilator does not complain about invalid parameter declaration #1424
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Original Redmine Comment Parameter without initial values are legal in SystemVerilog 2017, this is not disabled when requesting earlier versions (and you request a earlier version anyhow). I think everything is working as intended, except that the Internal Error should instead be a user error that the provided parameter was not provided (IEEE 2017 6.20.1). Agree? |
Original Redmine Comment From the referenced documentation it seems to me that initial value can be omitted only in exceptional cases, but I must confess that I am far from an expert. :) For my FPGA design I want to catch syntax errors and possible coding failures as soon as possible. For this I use verilator to lint sources before implementation that saves (and already saved) me lot of potential headaches. In the demonstrated case I get syntax error from the Xilinx syntheser after a successful linting with verilator. The aim of this issue was to point this out. More explicit I used this for linting:
Is it possible to add warning message for Verilog 2001? Or would it be overkill to implement this? |
Original Redmine Comment Makes sense. Will do this then:
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Original Redmine Comment Sounds perfect. Thank you! |
Original Redmine Comment Fixed in git towards 4.014. |
Original Redmine Comment In 4.014. |
Original Redmine Comment It works. Thank you very much! |
Author Name: Peter Gerst
Original Redmine Issue: 1424 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
Verilator fails to trow syntax error on parameter declaration without constant expression, like this:
See the following example codes.
parameter_lint.v:
parameter_main.v:
Verilator is called in the following way:
The command above finishes without error. If I comment out the assignment of param1 in instantiation of parameter_lint module in parameter_main.v I get internal error.
I used verilator release 4.012 built under cygwin.
Normally i used to call Verilator with specifying verilog 2001 language standard that needs constant expression in parameter declaration. (Xilinx syntheser i used supports this standard.) It seems to be valid for SystemVerilog 2017 as well (http://ecee.colorado.edu/~mathys/ecen2350/IntelSoftware/pdf/IEEE_Std1800-2017_8299595.pdf, page 120).
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