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I am using verilator to lint verilog modules which will be then synthesized by Xilinx tools. Prior to synthesis verilator is called with --lint-only mode to find errors and potential failures.
The following code makes Xinlinx syntheser to complain about signal re-declaration:
module output_wire (
input wire CLK,
input wire RESET,
input wire in0,
output wire out0,
output reg out1
);
wire out0;
reg out1;
assign out0 = (RESET) ? 1'b0 : in0;
always @(posedge CLK) begin
if (RESET) begin
out1 <= 1'b0;
end else begin
out1 <= in0;
end
end
endmodule
In contrast verilator does not warn about anything:
This module is found to be okay by verilator although the differently declared out1 but if I uncommented line "/* wire [1:0] out0; */" and commented line "reg [1:0] out1;" I got:
$ verilator --lint-only --default-language 1364-2001 -Wall -Wno-PINCONNECTEMPTY output_wire.v
%Warning-WIDTH: output_wire.v:16: Operator COND expects 2 bits on the Conditional True, but Conditional True's CONST '1'h0' generates 1 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: output_wire.v:16: Operator COND expects 2 bits on the Conditional False, but Conditional False's VARREF 'in0' generates 1 bits.
%Error: Exiting due to 2 warning(s)
%Error: Command Failed /usr/local/bin/verilator_bin --lint-only --default-language 1364-2001 -Wall -Wno-PINCONNECTEMPTY output_wire.v
Original Redmine Comment
Author Name: Peter Gerst
Original Date: 2019-06-17T10:11:34Z
I tried the first example with version 4.016 but it did not worked. Verilator did not raise warning or error on duplicated signals.
Verilator was compiled on cygwin 3.0.7 with gcc 7.4.0.
Author Name: Peter Gerst
Original Redmine Issue: 1462 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
I am using verilator to lint verilog modules which will be then synthesized by Xilinx tools. Prior to synthesis verilator is called with --lint-only mode to find errors and potential failures.
The following code makes Xinlinx syntheser to complain about signal re-declaration:
In contrast verilator does not warn about anything:
I also noticed that wire and reg signals are handled differently by verilator. See the following example:
This module is found to be okay by verilator although the differently declared out1 but if I uncommented line "/* wire [1:0] out0; */" and commented line "reg [1:0] out1;" I got:
verilator version:
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