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Optimize performance of bit operations by vectorizing #1542

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veripoolbot opened this issue Oct 6, 2019 · 0 comments
Open

Optimize performance of bit operations by vectorizing #1542

veripoolbot opened this issue Oct 6, 2019 · 0 comments
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area: performance Issue involves performance issues effort: weeks Expect this issue to require weeks or more of invested effort to resolve type: feature-non-IEEE Request to add new feature, outside IEEE 1800

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Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 1542 from https://www.veripool.org

Feature tracking bug.

Verilator at present only vectorizes some very simple assignments of the form

assign a[2] = foo[2]
assign a[3] = foo[3]

into e.g. a[3:2] = foo[3:2]. The V3Gate/V3Const process should be improved to vectorize general equations. There is probably some literature on this as is similar to normal code vectorization.

For some designs written at a low level expect a 5-30% performance improvement.
@veripoolbot veripoolbot added area: performance Issue involves performance issues effort: weeks Expect this issue to require weeks or more of invested effort to resolve type: feature-non-IEEE Request to add new feature, outside IEEE 1800 labels Dec 22, 2019
@wsnyder wsnyder changed the title Improve performance of bit operations by vectorizing Optimize performance of bit operations by vectorizing Mar 16, 2023
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area: performance Issue involves performance issues effort: weeks Expect this issue to require weeks or more of invested effort to resolve type: feature-non-IEEE Request to add new feature, outside IEEE 1800
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