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Warning-CASEOVERLAP is not triggering for signals wider than 12 #1545

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veripoolbot opened this issue Oct 7, 2019 · 2 comments
Open

Warning-CASEOVERLAP is not triggering for signals wider than 12 #1545

veripoolbot opened this issue Oct 7, 2019 · 2 comments
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area: data-types Issue involves data-types area: lint Issue involves SystemVerilog lint checking

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Author Name: Yossi Nivin
Original Redmine Issue: 1545 from https://www.veripool.org

Hi,

I noticed that I'm not getting the CASEOVERLAP warnings if the value is wider than 12 bits.
In the example below, the warning will trigger only for the second case, which uses the 12 bits input. The first case with 13 bits is ignored.

module top (
     input [12:0] case_input_13,
     input [11:0] case_input_12,
     output result_13,
     output result_12
);

     always_comb
         case (case_input_13)
             13'h0: result_13 = |case_input_13;
             13'h1: result_13 = |case_input_13;
             13'h2: result_13 = |case_input_13;
             13'h3: result_13 = |case_input_13;
             13'h0: result_13 = |case_input_13; // Case overlap
             default: result_13 = |case_input_13;
         endcase

     always_comb
         case (case_input_12)
             12'h0: result_12 = |case_input_12;
             12'h1: result_12 = |case_input_12;
             12'h2: result_12 = |case_input_12;
             12'h3: result_12 = |case_input_12;
             12'h0: result_12 = |case_input_12; // Case overlap
             default: result_12 = |case_input_12;
         endcase

endmodule

Steps to reproduce:
verilator -Wall -cc top.sv
@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-10-07T11:38:57Z

Currently the algorithm is very stupid, namely build a lookup table and check for duplicates.

I changed this define to something larger, e.g. 16 bits:

#define CASE_OVERLAP_WIDTH 12           // Maximum width we can check for overlaps in

(You can do that in your build if you want also).

Leaving this open as the real correct fix for this is to use a binary decision diagram or other better algorithm to prove the overlaps in a way that isn't so memory-stupid.

If you or someone would be interested, this would be a fun contained project to work on.

@veripoolbot
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Original Redmine Comment
Author Name: Yossi Nivin
Original Date: 2019-10-07T12:04:59Z

Thanks for confirming and providing the workaround.
I was suspecting this kind of lookup table to be the limiting factor.
I will try to have a look to see whether it is something I can implement with my limited knowledge of C/C++.

@veripoolbot veripoolbot added area: data-types Issue involves data-types area: lint Issue involves SystemVerilog lint checking labels Dec 22, 2019
@wsnyder wsnyder mentioned this issue May 3, 2020
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