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gives no output: everything is fine.
WebPack ISE 14.7 says:
Started : "Check Syntax for testmodule".
Running xst...
Command Line: xst -intstyle ise -ifn /home/jacko/git/ISEproject/testmodule.xst -ofn testmodule.stx
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "../../temp/testmodule.v" in library work
Module <testmodule> compiled
ERROR:HDLCompilers:247 - "../../temp/testmodule.v" line 37 Reference to vector wire 'val' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "../../temp/testmodule.v" line 37 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "../../temp/testmodule.v" line 39 Reference to vector wire 'val' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "../../temp/testmodule.v" line 39 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "../../temp/testmodule.v" line 41 Reference to vector wire 'val' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "../../temp/testmodule.v" line 41 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "../../temp/testmodule.v" line 43 Reference to vector wire 'val' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "../../temp/testmodule.v" line 43 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "../../temp/testmodule.v" line 45 Reference to vector wire 'val' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "../../temp/testmodule.v" line 45 Illegal left hand side of blocking assignment
Analysis of file <"testmodule.prj"> failed.
-->
Total memory usage is 457988 kilobytes
Number of errors : 10 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Check Syntax" failed
Which, to my limited knowledge, is a correct error: the val should be a register.
The text was updated successfully, but these errors were encountered:
Author Name: Jacko Dirks (@jackodirks)
Original Redmine Issue: 1570 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
I used the most recent master commit of verilator to show this problem exists in the current master branch.
Take the following verilog code:
The output @Val@ should contain the keyword reg. But verilator does not agree:
@verilator -Wall -cc testmodule.v --exe test_top.cpp --trace@
gives no output: everything is fine.
WebPack ISE 14.7 says:
Which, to my limited knowledge, is a correct error: the val should be a register.
The text was updated successfully, but these errors were encountered: