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Wrong modport directionality accross scopes doesn't trigger an error #1622

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veripoolbot opened this issue Dec 6, 2019 · 4 comments
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area: lint Issue involves SystemVerilog lint checking effort: days Expect this issue to require roughly days of invested effort to resolve

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@veripoolbot
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Author Name: Driss Hafdi
Original Redmine Issue: 1622 from https://www.veripool.org


Verilator doesn't seem to be able to assert the correctness of modport directionality when it involves multiple scope levels. This small testbench (drissos@2cec11a) illustrates the problem and passes in verilator where it should instead fail with an error message along this line:

     %Error: t/t_modport_direction_bad.v:36: Attempt to drive input-only modport: 'data'
     : ... In instance t.source_i.source_i
     ctrl.data <= ~ctrl.data;
     ^~~~
     %Error: Exiting due to 1 error(s)
     %Error: t/t_modport_direction_bad.v:37: Attempt to drive input-only modport: 'valid'
     : ... In instance t.source_i.source_i
     ctrl.valid<= ~ctrl.valid;
     ^~~~
     %Error: Exiting due to 1 error(s)
</code>
@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-06T22:27:49Z


Thanks for making the test case. Might you be able to look at fixing some of these? Anyhow I will also take a look.

@veripoolbot
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Original Redmine Comment
Author Name: Driss Hafdi
Original Date: 2019-12-06T23:11:19Z


Thanks for looking at all the issues. I'm not super familiar with the codebase, but would love to give it a try and learn in the process. Any suggestion on which one I should tackle first ?

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-07T17:58:28Z


Pushed the test_regress/t/t_interface_modport_dir_bad.v test with an unsupported() tag (so doesn't run).

@veripoolbot veripoolbot added area: lint Issue involves SystemVerilog lint checking effort: days Expect this issue to require roughly days of invested effort to resolve labels Dec 22, 2019
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wsnyder commented Nov 20, 2022

This got fixed a while ago.

@wsnyder wsnyder closed this as completed Nov 20, 2022
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area: lint Issue involves SystemVerilog lint checking effort: days Expect this issue to require roughly days of invested effort to resolve
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