Interface declared in parent scope can be used incorrectly #1623
Labels
area: elaboration
Issue involves elaboration phase
area: lint
Issue involves SystemVerilog lint checking
effort: days
Expect this issue to require roughly days of invested effort to resolve
Author Name: Driss Hafdi
Original Redmine Issue: 1623 from https://www.veripool.org
If an interface is declared in a module's parent scope, it seems as though the current scope can still use the interface instance as if it was declared locally. While it is a legal systemverilog construct (Section "23.8 Upwards name referencing" in the LRM), it doesn't bode well with synthesis and a warning would be ideal. Here is an small testbench that exposes this issue: drissos@046205a
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