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Question: AUTOINSTPARAM use with dependent parameters #1663

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veripoolbot opened this issue Feb 28, 2020 · 7 comments
Closed

Question: AUTOINSTPARAM use with dependent parameters #1663

veripoolbot opened this issue Feb 28, 2020 · 7 comments
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Author Name: Berk Akinci
Original Redmine Message: 3215 from https://www.veripool.org

Hi,
I often find myself with parameterized modules with dependent parameters. They can't be localized because they affect ports (and I'm still using Verilog 2001).

In the below example, I'd like ideally to have user module to only have @BYTES_PER_WORD@ exposed and all else calculated. (I do have a bit of dilemma on how complicated an expression I would tolerate in the brackets.)
I saw that you recently added a regex to AUTOINSTPARAM, but then the undeclared parameters are used in the module instance ports.

Do you have a suggested use in this case w/ numerous dependent parameters?

I'm probably asking for a little too much automation, but I ask in case you have already solved this in a way I haven't discovered.

Thanks,

Berk

Here's a simplified example:

module multiplier
  #(// Parameters                                                                                                       
     parameter BYTES_PER_WORD = 4,                                                                                       
     parameter BITS_IN        = 8 * BYTES_PER_WORD,                                                                             
     parameter BITS_OUT       = 2 * BITS_IN                                                                                    
     )
    (// Outputs                                                                                                          
     output reg [BITS_OUT-1:0] out,
     // Inputs                                                                                                           
     input [BITS_IN-1:0]       in_a,
     input [BITS_IN-1:0]       in_b
     /*AUTOARG*/);

    always @* begin : Combinational_Multiplier_Example
       out = in_a * in_b;
    end

endmodule // multiplier                                                                                                 


module example
  ();
    multiplier
      #(/*AUTOINSTPARAM*/)
    multiplier_instance
      #(/*AUTOINST*/);

endmodule // example
@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2020-02-29T03:20:35Z

I'd suggest don't use ANSI style arguments, instead use 1995 style, and 2001's localparam:

module multiplier
  #(// Parameters                                                                                        
     parameter BYTES_PER_WORD = 4)
    (/*AUTOARG*/);

     localparam BITS_IN        = 8 * BYTES_PER_WORD,
     localparam BITS_OUT       = 2 * BITS_IN

     output reg [BITS_OUT-1:0] out,
     input [BITS_IN-1:0]       in_a,
     input [BITS_IN-1:0]       in_b

@veripoolbot
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Original Redmine Comment
Author Name: Berk Akinci
Original Date: 2020-02-29T16:58:12Z

Oooh. Thanks! I hadn't though of looking backward.
I'll see how to work this into my "style."

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Original Redmine Comment
Author Name: Berk Akinci
Original Date: 2020-02-29T17:07:41Z

Foiled!
The /AUTOINST/ expansion still refers to @BITS_IN@ etc even with verilog-auto-inst-param-value:t.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2020-02-29T17:21:41Z

I think you used "parameter" instead of "localparam".

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Original Redmine Comment
Author Name: Berk Akinci
Original Date: 2020-02-29T17:33:16Z

I only used parameter for the @BYTES_PER_WORD@. I noticed I hadn't given a number to that parameter on the upper module.
I even split them to proper two-files.
May be it's because I have a mix of ANSI-style parameters and Verilog-1995-style ports.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2020-02-29T17:55:44Z

I misunderstood what you said was wrong in the last exchange, at present verilog-mode doesn't parse the value of the "inner" localparam, so won't do what you want.

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Original Redmine Comment
Author Name: Berk Akinci
Original Date: 2020-02-29T18:03:16Z

I was thinking that's a lot of language awareness for verilog-mode...
I know you've said in the past may be some day verilog-mode will parse and propagate default parameters. I think that would solve my issue (partially.) It still doesn't solve the @BITS_OUT@ being dependent on @BITS_IN@. But with that knowledge, I can form my parameter expressions more appropriately.
Anyway. Thanks for making and maintaining verilog-mode. It makes life a lot better.

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