Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Question: AUTOINPUTEVERY #826

Closed
veripoolbot opened this issue Oct 1, 2014 · 1 comment
Closed

Question: AUTOINPUTEVERY #826

veripoolbot opened this issue Oct 1, 2014 · 1 comment
Labels
question

Comments

@veripoolbot
Copy link
Collaborator

Author Name: Vinod B
Original Redmine Message: 1439 from https://www.veripool.org

Is it possible to have an AUTOINPUTEVERY option just like AUTOOUTPUTEVERY such that every signal on the right hand side of a wire assignment is automatically made an input port?
@veripoolbot
Copy link
Collaborator Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-10-01T19:10:13Z

Not easily, as at present verilog-mode does not parse any right hand sides of the assignments.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
question
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@veripoolbot