Introduction to Verilog-Mode¶
Written by Michael McNamara <firstname.lastname@example.org> and Wilson Snyder <email@example.com>.
Verilog-mode.el is the extremely popular free Verilog mode for Emacs which provides context-sensitive highlighting, auto indenting, and provides macro expansion capabilities to greatly reduce Verilog coding time. It supports AUTOs and indentation in Emacs for traditional Verilog (1394-2005), the Open Verification Methodology (OVM) and SystemVerilog (1800-2005/1800-2009).
Recent versions allow you to insert AUTOS in non-AUTO designs, so IP interconnect can be easily modified. You can also expand SystemVerilog ".*" port instantiations, to see what ports will be connected by the simulators.
Verilog-mode.el is being used by thousands of engineers world wide. The Verilog AUTOS are in use by many of the leading IP providers, including IP processor cores sold by MIPS and Arm.
See the buttons at the top of this page, which include:
Note to Searchers¶
If you're looking for Verylog-mode or an Emacs mode for Verylog HDL, this is it, you just need to correct your spelling. :) Also, some people search for systemverilog-mode or system-verilog-mode for Emacs; Verilog-mode is what you want, we wrote Verilog-Mode before SystemVerilog was named.