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This page describes some of the general technical papers and presentations produced by the contributors on this site. Please contact the author if what you are looking for is missing from this list.


Title Date Place Tool Description
Verilator Internals 1 [Slides] 2020-10 Private Verilator Internal structures and debugging of Verilator. By Wilson Snyder.
Verilator, Accelerated [Video]
Verilator, Accelerated [Slides]
2020-04 OSDA 2020 Verilator The accelerated development of Verilator with case study of accelerating SweRV core. By Wilson Snyder.
SystemVerilog Tedium [Slides] 2020-04 Marvell Engineering Verilog-Mode Using Verilog-mode to simplify SystemVerilog coding. By Wilson Snyder. See also Verilog-Mode.
Ten Creative Uses for Verilator [Slides] 2019-11 CHIPS Tools 2019 Verilator Verilator for non-traditional tasks. By Wilson Snyder.
DPI Protected Verilog Instead of Encryption: A non-broken and open source friendly alternative to IEEE-1735 [Slides] 2019-09 ORConf 2019 Verilator Using Verilator --dpi-protect and futures. By Todd Strader.
Verilator: Your Big 4th Simulator 2019 Intro and Roadmap [Slides] 2019-06 CHIPS Alliance 2019 Verilator Verilator intro and futures. By Wilson Snyder.
Verilator 4.0: Open Simulation Goes Multithreaded [Video]
Verilator 4.0: Open Simulation Goes Multithreaded [Slides]
2018-09 ORConf2018 Verilator Verilator 4.0 features and multithreading. By Wilson Snyder.
Verilator: Speedy Reference Models, Direct from RTL [Slides] 2017-10 University of Massachusetts Amherst Verilator Using Verilator for reference modeling, and futures. By Wilson Snyder.
Verilator: Open Simulation Growing Up [Slides] 2013-01 DVClub Bristol Verilator Recent Verilator changes and contributing back. By Wilson Snyder.
Verilog Preprocessor: Force for `Good and `Evil [Slides], Verilog Preprocessor: Force for `Good and `Evil [Paper] 2010-09 SNUG Boston Verilog-Perl Best practices and techniques for the preprocessor, and vppreproc, by Wilson Snyder. Won 3rd Best Paper. See also Vppreproc.
Verilator: Fast, Free, but for Me? [Slides] 2010-09 DVClub Bristol Verilator Open sourced simulator advantages, downsides. Introduction and tips on using Verilator, and other Veripool tools. By Wilson Snyder.
Measuring Active Power Using PT-PX: A User Perspective [Paper] 2010-09 SNUG Boston - Using PrimeTime PX (PT PX) to measure active power, including conditions under which the generated power numbers are inaccurate and strategies to avoid these pitfalls. By Duane E. Galbi, Karthik Kannan.
Verilog-Mode AUTOs Update [Slides] 2009-09 Cavium Networks Verilog-Mode Update on recent Verilog-mode features. By Wilson Snyder. See also Verilog-Mode.
CovVise: How We Stopped Throwing Away Interesting Coverage Data [Paper], CovVise: How We Stopped Throwing Away Interesting Coverage Data [Slides] 2009-09 Synopsys User's Group Boston CovVise CovVise philosophy and program overview. By Wilson Snyder.
Test ER: Triage Millions of Tests [Slides] 2007-10 Design Verification Club Boston - Our future work on writing BugVise to automatically triage test run failures. By Wilson Snyder. See also BugVise.
Ten IP Edits [Paper], Ten IP Edits [Slides] 2007-09 Synopsys User's Group Boston - RTL Edits commonly made to integrate IP. Won best Technical Paper. By Wilson Snyder.
SiCortex Functional Verification [Paper], SiCortex Functional Verification [Slides] 2007-06 DAC Verilator Techniques and tools used to verify the SiCortex System on a Chip. By Oleg Petlin.
Verilator Internals [Slides] 2005-07 Philips Semiconductors Verilator The history, usage, and some internals of Verilator. By Wilson Snyder. See also Verilator.
Verilator SystemC Environment [Slides] 2004-06 North American SystemC User's Group/ DAC Verilator Using Verilator inside a SystemC environment. By Wilson Snyder. See also Verilator.
505 Registers or Bust [Paper], 505 Registers or Bust [Slides] 2001-08 Synopsys User's Group Boston - Using Vregs to capture register declarations from specifications. By Wilson Snyder. See also Vregs.
Veritedium [Paper], Veritedium [Slides] 2001-03 (Updated 2006-01) San Jose Synopsys User's Group Verilog-Mode (See 2009-09 for newer version.) Using Verilog-mode to simplify Verilog coding. By Wilson Snyder. See also Verilog-Mode.
Synthesisizable Watchdog Logic [Paper], Synthesisizable Watchdog Logic [Slides] 2000 Synopsys User's Group Boston Verilog-Perl Using Vpassert to insert assertions. By Duane Galbi. Won the Best Technical Paper award. See also Verilog-Perl.
Boa Methodology [Paper], Boa Methodology [Slides] 1997-02 Synopsys User's Group (San Jose and Europe) - Early synthesis methodology allowing easy signal time budgeting.