Veripool

Verilator Documentation

Program Documentation

Announcements

To get notified of new releases and other important announcements, go to Verilator announcement repository and follow the instructions there.

Commercial Support

See Commercial Support.

Tutorials

High Performance SoC Modeling with Verilator - A Tutorial for Cycle Accurate SystemC Model Creation and Optimization using Verilator. Authors: Jeremy Bennett of Embecosm. Includes tips on optimizing performance and removing compile warnings.
Verilator Waivers - Verilator Wavers. Authors: Stefan Wallentowitz. How to efficiently maintain lint waivers.

Papers on Verilator Specifically

Verilator's Wikipedia entry - See paper references at end of the article.

Most recent paper first:

Support for Upstream UVM 2017 in Verilator - Details effort to add full UVM 2017 support to Verilator, including dynamic scheduling, coroutine-based execution, constrained randomization, and UVM Cookbook example compatibility. Authors: Antmicro on October 2025.
Enhancing RTL Coverage Reporting in Verilator - Explains enhancements to Verilator's coverage engine, and use with Coverview tool. Authors: Antmicro on August 2025.
Improving Verilator's Hierarchical Mode for Better Performance and Scalability - Explains improvements to hierarchical Verilation. Authors: Antmicro on May 2025.
Constrained Randomization in Verilator: Implementation Details - Outlines engineering of constrained randomization support in Verilator as part of broader UVM enhancements. Authors: Antmicro on August 2024.
Initial Assertion Control Support in Verilator - Introduces global assertion API in Verilator, and typical assertion use cases. Authors: CHIPS Alliance / Antmicro contributors on June 2024.
Analyze Verilator processes and ASTs with the astsee suite - Introduces astsee, a toolkit to visualize and debug Verilator's internal Abstract Syntax Tree (AST). Authors: Antmicro on January 2024.
Open Source Design Testing and Verification with UVM and Verilator - Status of UVM support in Verilator. Authors: Krzysztof Bieganski of Antmicro to ORConf 2023.
UVM + Verilator - Open source effort demonstrating UVM testbenches running on Verilator, used in broader RISC-V and SoC verification stacks. Authors: Antmicro on October 2023.
Verilator Model Generation Performance Improvements & Initial Multithreaded Verilation Support - Summarizes improving Verilator's memory usage, runtime type analysis, and multithreaded verilation passes. Authors: CHIPS Alliance Tools Workgroup, Antmicro on September 2023.
Progress in open source SystemVerilog / UVM support in Verilator - Status report on the roadmap to UVM support. Authors: Antmicro on January 2023.
Coroutines for Dynamic Scheduling in Verilator - Update on project to add UVM-capable scheduling to Verilator. Author: Antmicro on December 2021.
What You Need to Know About Verilator Open Source Tooling - Article summarizing the importance of Verilator in the RISC-V ecosystem, and collaboration between CHIPS Alliance and Antmicro to improve Verilator. Authors: Rob Mains on July 2021.
Dynamic Scheduling in Verilator - Project to add UVM-capable scheduling to Verilator. Author: Antmicro on June 2021.
Verilator Internals 1 - Internal structures and debugging of Verilator. Author: {{WSNYDER}} on October 2020.
Verilator, Accelerated - The accelerated development of Verilator with case study of accelerating SweRV core. Author: {{WSNYDER}} to OSDA 2020.
Verilator Your Big 4th Simulator 2019 Intro and Roadmap - Verilator intro and futures. CHIPS Alliance 2019.
DPI Protected Verilog Instead of Encryption: A non-broken and open source friendly alternative to IEEE-1735 [pdf] - Using Verilator's --protect-lib for IP. Author: Todd Strader to ORConf 2019.
Ten Creative Uses for Verilator - Verilator for non-traditional tasks. CHIPS Tools 2019.
Verilator 4.0: Open Simulation Goes Multithreaded [pdf] - Verilator 4.0 features and multithreading. Author: {{WSNYDER}} to ORConf 2018.
Verilator: Open Simulation - Growing Up [pdf] - Recent changes in Verilator and contributing back. Author: {{WSNYDER}} to 2013 DVClub Bristol.
Verilator: Fast, Free, but for Me? [pdf] - Presentation on open sourced simulator advantages, downsides. Introduction and tips on using Verilator, and other Veripool tools. Author: {{WSNYDER}} to 2010 DVClub Bristol.
Verilator Internals Slides [pdf] - A presentation on history, usage, and some internals of Verilator. Author: {{WSNYDER}} to Philips Semiconductors in July 2005.
Verilator SystemC Environment Slides [pdf] - A paper on using Verilator inside a SystemC environment. Author: {{WSNYDER}} to the 2004 North American SystemC User's Group part of the Design Automation Conference.
Verilator: Speedy Reference Models, Direct from RTL [pdf] - Reference models, using Verilator, and some possible future directions. Author: {{WSNYDER}} to University of Massachusetts Amherst on 2017.

Other Papers Using Verilator

In alphabetical order:

A Case for Accelerating Software RTL Simulation - Optimizations to improve cycle simulation, including Verilator benchmarks. Authors: Scott Beamer.
Amplify ML Hardware Design Productivity with TVM-driven Hardware Simulation - Verilating into a ML framework
Atmel and the use of Verilator to create uC Device Models - Atmel present on their use of Verilator. Authors: Dag Braend, Roland Kruse, Jie Xu, and Jan Egil Ruund.
Caliptra: Building Open Source Security IP with Open Source Tools ORConf 2023 Archive - Outlines the Caliptra Root of Trust use of Verilator as a central component of the verification strategy. Authors: Michael Gielda of Antmicro at OrConf 2023.
Co-simulating HDL models in Renode with Verilator - Capability to import Verilator models into Renode. Author: Antmicro September 2019.
Debugging and Verifying SoC Designs Through Effective Cross-Layer Hardware-Software Co-Simulation - Using Verilator to convert Chisel-generated Verilog into C++ models, and resulting speedup benchmarks. Keith Campbell, et al at U of Illinois, Nanyang Technological University, and Advanced Digital Science Center Singapore on June 2016.
Developing Silicon IP with Open Source Tools - Paper on economies of using Verilator and CovVise. Authors: Arthur Low.
On Fault-Effect Analysis at the Virtual Prototype Abstraction Level - Fault injection with Verilator. Authors: Bogdan-Andrei Tabacaru.
Open-Source UVM Verification of AXI Systems in Verilator - Describes verifying AXI-based systems using UVM testbenches running on Verilator. Authors: Antmicro on September 2024.
Parallel Multi-core Verilog HDL Simulation based on Domain Partitioning - Using Verilator for parallelized gate simulations. Authors: Tariq B. Ahmad, Maciej Ciesielski.
Porting a Complete UVC to Verilator + UVM – an anecdote! - Using UVM+Verilator with third-party VIP. Author: AsFigo on November 2023.
Renode Bazel Rules for Advanced Co-simulation Scenarios - Build system integration using Bazel to manage complex co-simulations, using Verilator DPI (Direct Programming Interface). Authors: Antmicro on November 2025.
Taking a New Look at Verilator - Tutorial on using Verilator and a C++ testbench, with links to ZipCPU, UART, Flash controller and other examples. Authors: Dan Gisselquist.
Using Verilator for Processor Benchmarking of Automotive SoC Platforms - Verilating to SystemC for use in Synopsys Platform Architect. Authors: Johannes Sanwald et al to DVCON Europe 2024.
Verifying Verification: Using Open Source to Roll Your Own - Using Verilator to do mutation analysis similar to Certitude. Authors: David Hewson.

Notable Projects Encapsulating or Extending Verilator

In alphabetical order:

Apache TVM Open Deep Learning Compiler Stack - Compiler stack for deep learning integrating Verilated models
Chisel - Chisel hardware language has Verilator backend.
Cocotb Simulator Support - Technical reference on using Verilator when used with the Python-based Cocotb verification framework. Authors: Cocotb Maintainers.
Extending Verilator to Enable Fault Simulation - Techniques for adding fault-injection capabilities to Verilator to evaluate safety-critical designs, documenting performance and validation methodology. Authors: Endri Kaja, et al.
FuseSoC - Package manager and build tools including Verilator support
PRO-V: Reasoning Enhanced Programming Agent for RTL Verification - AI-driven multi-agent system for RTL verification using Verilator as the underlying simulation engine. Authors: Yujie Zhao et al. at UCSD on December 2025.
PyMTL3 (Mamba) - PyMTL open-source Python-based hardware generation, simulation, and verification framework
Simopt-Power: Leveraging Simulation Metadata for Low-Power - Describes Simopt-power, a method for estimating power consumption using Verilator simulation metadata. Authors: Eashan Wadhwa, Shanker Shreejith, at Trinity College Dublin on October 2025.
Verilog Playground - SystemVerilog online simulator, using Verilator to convert to C++, then Emscripten to convert to JavaScript
VeriSide: A Modified Verilator for Leakage Assessment at the RTL Level - Introduces "VeriSide" which uses modified Verilator internals to generate side-channel leakage information (power/electromagnetic) directly during simulation, avoiding the need for VCD files. Authors: Behnam Farnaghinejad et al, at Politecnino di Torino on December 2025.
vmodel - Tool to simulate Verilated Verilog modules inside MATLAB simulations.

Notable Projects Using Verilator as a Simulator

In alphabetical order:

80186 core by Jamie Iles - 80186 verified with Verilator, and Verilator to cobertura coverage importer.
An open source SystemVerilog Test Suite - Introduces sv-tests, a compliance test suite for SystemVerilog tools, used to test Verilator's language support. Authors: Antmicro on November 2019.
Caliptra - Root of Trust by CHIPS Alliance and Open Compute .
CERN SoC design platform - Use of Verilator in Readiation Tolerant SoC Ecosystem. By Risto Pejasinovic on October 2003.
Ibex - 32-bit RISC-V core
OpenTitan / lowRISC - Open source root-of-trust builds with Verilator, FuseSoC and Bazel.
RISC-V Contest - Contest sponsored by Google, Antmicro, Lattice Semiconductor and Microsemi, requires use of Verilator in all submissions.
Tesla Hot Chips 2019 - Tesla reports ~30x speedup using Verilator. Hot Chips 2019.
VeeR RISC-V Cores - Open-sourced high and low performance RISC-V cores.
ZipCPU - 32 bit processor verified with Verilator.
Many, many more on github and OpenCores, among others.