This collects general technical papers and presentations produced by the contributors on this site. Please contact the author if what you are looking for is missing from this list.
| Verilator Internals 1 (Slides) | 2020-10 | Internal structures and debugging of Verilator. By Wilson Snyder. |
| Verilator, Accelerated (Video) + Verilator, Accelerated (Slides) | 2020-04 @ OSDA 2020 | The accelerated development of Verilator with case study of accelerating SweRV core. By Wilson Snyder. |
| SystemVerilog Tedium (Slides) | 2020-04 @ Marvell Engineering | Using Verilog-mode to simplify SystemVerilog coding. By Wilson Snyder. See also /verilog-mode |
| Ten Creative Uses for Verilator (Slides) | 2019-11 @ CHIPS Alliance | Verilator for tasks beyond simulation and linting. By Wilson Snyder. |
| DPI Protected Verilog Instead of Encryption: A non-broken and open source friendly alternative to IEEE-1735 (Slides) | 2019-09 @ ORConf 2019 | Using Verilator --dpi-protect and futures. By Todd Strader. |
| Verilator: Your Big 4th Simulator: 2019 Intro and Roadmap (Slides) | 2019-06 @ CHIPS Alliance | Verilator intro and futures. By Wilson Snyder. |
| Verilator 4.0: Open Simulation Goes Multithreaded (Video) + Verilator 4.0: Open Simulation Goes Multithreaded (Slides) | 2018-09 @ ORConf2018 | Verilator 4.0 features and multithreading. By Wilson Snyder. |
| Verilator: Speedy Reference Models, Direct from RTL (Slides) | 2017-10 @ U Mass Amherst | Using Verilator for reference modeling, and futures. By Wilson Snyder. |
| Verilator: Open Simulation Growing Up (Slides) | 2013-01 @ DVClub Bristol | Recent Verilator changes and contributing back. By Wilson Snyder. |
| Verilog Preprocessor: Force for Good and Evil (Slides) + Verilog Preprocessor: Force for Good and Evil (Paper) | 2010-09 @ SNUG Boston | Best practices and techniques for the preprocessor, and vppreproc, by Wilson Snyder. Won 3rd Best Paper. See also /wiki/verilog-perl.[Vppreproc] |
| Verilator: Fast, Free, but for Me? (Slides) | 2010-09 @ DVClub Bristol | Open sourced simulator advantages, downsides. Introduction and tips on using Verilator, and other Veripool tools. By Wilson Snyder. |
| Measuring Active Power Using PT-PX: A User Perspective (Paper) | 2010-09 @ SNUG Boston | Using PrimeTime PX (PT PX) to measure active power, including conditions under which the generated power numbers are inaccurate and strategies to avoid these pitfalls. By Duane E. Galbi, Karthik Kannan. |
| Verilog-Mode AUTOs Update (Slides) | 2009-09 @ Cavium Networks | Update on recent Verilog-mode features. By Wilson Snyder. See also /wiki/verilog-mode.[Verilog-Mode] |
| CovVise: How We Stopped Throwing Away Interesting Coverage Data (Paper) + CovVise: How We Stopped Throwing Away Interesting Coverage Data (Slides) | 2009-09 @ SNUG Boston | CovVise philosophy and program overview. By Wilson Snyder. |
| Test ER: Triage Millions of Tests (Slides) | 2007-10 @ DVClub Boston | Our future work on writing BugVise to automatically triage test run failures. By Wilson Snyder. |
| Ten IP Edits (Paper) + Ten IP Edits (Slides) | 2007-09 @ SNUG Boston | RTL Edits commonly made to integrate IP. Won best Technical Paper. By Wilson Snyder. |
| SiCortex Functional Verification (Paper) + SiCortex Functional Verification (Slides) | 2007-06 @ DAC | Techniques and tools used to verify the SiCortex System on a Chip. By Oleg Petlin. |
| Verilator Internals (Slides) | 2005-07 @ Philips Semiconductors | The history, usage, and some internals of Verilator. By Wilson Snyder. See also /wiki/verilator.[Verilator] |
| Verilator SystemC Environment (Slides) | 2004-06 @ North American SystemC User's Group/ DAC | Using Verilator inside a SystemC environment. By Wilson Snyder. See also /wiki/verilator.[Verilator] |
| 505 Registers or Bust (Paper) + 505 Registers or Bust (Slides) | 2001-08 @ SNUG Boston | Using Vregs to capture register declarations from specifications. By Wilson Snyder. See also /wiki/vregs.[Vregs] |
| Veritedium (Paper) + Veritedium (Slides) | 2001-03 (Updated 2006-01) @ SNUG San Jose | (See 2009-09 for newer version.) Using Verilog-mode to simplify Verilog coding. By Wilson Snyder. See also /wiki/verilog-mode.[Verilog-Mode] |
| Synthesisizable Watchdog Logic (Paper) + Synthesisizable Watchdog Logic (Slides) | 2000 @ SNUG Boston | Using Vpassert to insert assertions. By Duane Galbi. Won the Best Technical Paper award. See also /wiki/verilog-perl.[Verilog-Perl] |