Verilator Documentation


To get notified of new releases and other important announcements, go to Verilator announcement repository and follow the instructions there.

Commercial Support


  • High Performance SoC Modeling with Verilator - A Tutorial for Cycle Accurate SystemC Model Creation and Optimization using Verilator. By Jeremy Bennett of Embecosm. Includes tips on optimizing performance and removing compile warnings.
  • Verilator Waivers - Verilator Wavers. By Stefan Wallentowitz. How to efficiently maintain lint waivers.


Papers on Verilator Specifically

Other Papers Using Verilator

In alphabetical order:

Notable Projects Encapsulating Verilator

In alphabetical order:

  • Apache TVM Open Deep Learning Compiler Stack - Compiler stack for deep learning integrating Verilated models
  • Chisel - Chisel hardware language has Verilator backend
  • FuseSoC - Package manager and build tools including Verilator support
  • PyMTL3 (Mamba) - PyMTL open-source Python-based hardware generation, simulation, and verification framework
  • Verilog Playground - SystemVerilog online simulator, using Verilator to convert to C++, then Emscripten to convert to JavaScript
  • vmodel - Tool to simulate Verilated Verilog modules inside MATLAB simulations.

Notable Projects Using Verilator as a Simulator

In alphabetical order:

  • Jamie Iles 80186 core - 80186 verified with Verilator, and Verilator to cobertura coverage importer.
  • OpenTitan - Open source root-of-trust builds with Verilator
  • RISC-V Contest - Contest sponsored by Google, Antmicro, Lattice Semiconductor and Microsemi, requires use of Verilator in all submissions.
  • SweRV RISC-V Cores - Open-sourced high and low performance RISC-V cores
  • ZipCPU - 32 bit processor verified with Verilator.
  • Many, many more on github and OpenCores, among others.