This page contains documentation extracted from verilog-mode, revision 2024-11-07-06d4b20-vpo. Functions are described here beginning with verilog-mode and verilog-auto, then alphabetically.
See also the other Verilog-mode Documentation
You may copy this document, but it will soon get out of date; you are thus better linking to &BASE;verilog-mode-help.html, or getting these pages from the Emacs help system.
Copyright 2006, the Free Software Foundation. By Michael McNamara (mac@verilog.com). and Wilson Snyder (wsnyder@wsnyder.org).
Verilog
Expand AUTO statements. Look for any /*AUTO...*/ commands in the code, as used in instantiations or argument headers. Update the list of signals following the /*AUTO...*/ command.
Use M-x verilog-delete-auto to remove the AUTOs.
Use M-x verilog-diff-auto to see differences in AUTO expansion.
Use M-x verilog-inject-auto to insert AUTOs for the first time.
Use M-x verilog-faq for a pointer to frequently asked questions.
For new users, we recommend setting verilog-case-fold to nil
and verilog-auto-arg-sort to t.
The hooks verilog-before-auto-hook and verilog-auto-hook are
called before and after this function, respectively.
For example:
module ExampModule (/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/*AUTOREG*/
InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
endmodule
You can also update the AUTOs from the shell using:
emacs --batch <filenames.v> -f verilog-batch-auto
Or fix indentation with:
emacs --batch <filenames.v> -f verilog-batch-indent
Likewise, you can delete or inject AUTOs with:
emacs --batch <filenames.v> -f verilog-batch-delete-auto
emacs --batch <filenames.v> -f verilog-batch-inject-auto
Or check if AUTOs have the same expansion
emacs --batch <filenames.v> -f verilog-batch-diff-auto
Using M-x describe-function, see also:
verilog-auto-arg for AUTOARG module instantiations
verilog-auto-ascii-enum for AUTOASCIIENUM enumeration decoding
verilog-auto-assign-modport for AUTOASSIGNMODPORT assignment to/from modport
verilog-auto-inout for AUTOINOUT making hierarchy inouts
verilog-auto-inout-comp for AUTOINOUTCOMP copy complemented i/o
verilog-auto-inout-in for AUTOINOUTIN inputs for all i/o
verilog-auto-inout-modport for AUTOINOUTMODPORT i/o from an interface modport
verilog-auto-inout-module for AUTOINOUTMODULE copying i/o from elsewhere
verilog-auto-inout-param for AUTOINOUTPARAM copying params from elsewhere
verilog-auto-input for AUTOINPUT making hierarchy inputs
verilog-auto-insert-lisp for AUTOINSERTLISP insert code from lisp function
verilog-auto-insert-last for AUTOINSERTLAST insert code from lisp function
verilog-auto-inst for AUTOINST instantiation pins
verilog-auto-star for AUTOINST .* SystemVerilog pins
verilog-auto-inst-param for AUTOINSTPARAM instantiation params
verilog-auto-logic for AUTOLOGIC declaring logic signals
verilog-auto-output for AUTOOUTPUT making hierarchy outputs
verilog-auto-output-every for AUTOOUTPUTEVERY making all outputs
verilog-auto-reg for AUTOREG registers
verilog-auto-reg-input for AUTOREGINPUT instantiation registers
verilog-auto-reset for AUTORESET flop resets
verilog-auto-sense for AUTOSENSE or AS always sensitivity lists
verilog-auto-tieoff for AUTOTIEOFF output tieoffs
verilog-auto-undef for AUTOUNDEF `undef of local `defines
verilog-auto-unused for AUTOUNUSED unused inputs/inouts
verilog-auto-wire for AUTOWIRE instantiation wires
verilog-read-defines for reading `define values
verilog-read-includes for reading `includes
If you have bugs with these autos, please file an issue at URL `https://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR Wilson Snyder (wsnyder@wsnyder.org).
If true, treat signals matching this regexp as active low.
This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
you will probably also need verilog-auto-reset-widths set.
Hook run after verilog-save-font-no-change-functions restores highlighting.
Non-nil means align expressions of continuous assignments.
Distance (in spaces) between longest declaration/expression and comments.
Only works if verilog-align-decl-expr-comments is non-nil.
Non-nil means align declaration and expressions comments.
Non-nil means align `else' under matching `if'. Otherwise else is lined up with first character on line holding matching if.
Regexp that matches user typedefs for declaration alignment.
List of words that match user typedefs for declaration alignment.
Text used for delays in delayed assignments. Add a trailing space if set.
Expand AUTOARG statements. Replace the argument declarations at the beginning of the module with ones automatically derived from input and output statements. This can be dangerous if the module is instantiated using position-based connections, so use only name-based when instantiating the resulting module. Long lines are split based on the `fill-column', see M-x set-fill-column.
Limitations:
Typedefs must match verilog-typedef-regexp, which is disabled by default.
For example:
module ExampArg (/*AUTOARG*/);
input i;
output o;
endmodule
Typing M-x verilog-auto will make this into:
module ExampArg (/*AUTOARG*/
// Outputs
o,
// Inputs
i);
input i;
output o;
endmodule
The argument declarations may be printed in declaration order to
best suit order based instantiations, or alphabetically, based on
the verilog-auto-arg-sort variable.
Formatting is controlled with verilog-auto-arg-format variable.
Any ports declared between the ( and /*AUTOARG*/ are presumed to be predeclared and are not redeclared by AUTOARG. AUTOARG will make a conservative guess on adding a comma for the first signal, if you have any ifdefs or complicated expressions before the AUTOARG you will need to choose the comma yourself.
Avoid declaring ports manually, as it makes code harder to maintain.
Formatting to use for AUTOARG signal names. If `packed', then as many inputs and outputs that fit within `fill-column' will be put onto one line.
If `single', then a single input or output will be put onto each line.
Non-nil means AUTOARG signal names will be sorted, not in declaration order. Declaration order is advantageous with order based instantiations and is the default for backward compatibility. Sorted order reduces changes when declarations are moved around in a file, and it's bad practice to rely on order based instantiations anyhow.
See also verilog-auto-inst-sort.
Expand AUTOASCIIENUM statements, as part of M-x verilog-auto. Create a register to contain the ASCII decode of an enumerated signal type. This will allow trace viewers to show the ASCII name of states.
First, parameters are built into an enumeration using the synopsys enum comment. The comment must be between the keyword and the symbol. (Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
Next, registers which that enum applies to are also tagged with the same enum.
Finally, an AUTOASCIIENUM command is used.
The second parameter is the name to store the ASCII code into. For the signal foo, I suggest the name _foo__ascii, where the leading _ indicates a signal that is just for simulation, and the magic characters _ascii tell viewers like Dinotrace to display in ASCII format.
The third optional parameter is a string which will be removed from the state names. It defaults to "" which removes nothing.
The fourth optional parameter is "onehot" to force one-hot decoding. If unspecified, if and only if the first parameter width is 2^(number of states in enum) and does NOT match the width of the enum, the signal is assumed to be a one-hot decode. Otherwise, it's a normal encoded state vector.
verilog-auto-wire-type may be used to change the datatype of
the declarations.
"synopsys enum" may be used in place of "auto enum".
An example:
//== State enumeration
parameter [2:0] // auto enum state_info
SM_IDLE = 3\='b000,
SM_SEND = 3\='b001,
SM_WAIT1 = 3\='b010;
//== State variables
reg [2:0] /* auto enum state_info */
state_r; /* auto state_vector state_r */
reg [2:0] /* auto enum state_info */
state_e1;
/*AUTOASCIIENUM("state_r", "state_ascii_r", "SM_")*/
Typing M-x verilog-auto will make this into:
...
/*AUTOASCIIENUM("state_r", "state_ascii_r", "SM_")*/
// Beginning of automatic ASCII enum decoding
reg [39:0] state_ascii_r; // Decode of state_r
always @(state_r) begin
case ({state_r})
SM_IDLE: state_ascii_r = "idle ";
SM_SEND: state_ascii_r = "send ";
SM_WAIT1: state_ascii_r = "wait1";
default: state_ascii_r = "%Erro";
endcase
end
// End of automatics
Expand AUTOASSIGNMODPORT statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified interface and modport and use to build assignments into the modport, for making verification modules that connect to UVM interfaces.
The second parameter is a regexp of modports to read from in that interface.
The third parameter is the instance name to use to dot reference into.
The optional fourth parameter is a regular expression, and only signals matching the regular expression will be included.
The optional fifth parameter is a prefix to add to the signals.
Limitations:
verilog-auto-inst.
Inouts are not supported, as assignments must be unidirectional.
If a signal is part of the interface header and in both a modport and the interface itself, it will not be listed. (As this would result in a syntax error when the connections are made.)
See the example in verilog-auto-inout-modport.
Non-nil specifies the data type to use with verilog-auto-input etc.
Set this to "wire" if the Verilog code uses "`default_nettype
none". Note using `default_nettype none isn't recommended practice; this
mode is experimental.
Non-nil means to `delete-trailing-whitespace' in verilog-auto.
Non-nil means insert a comment /* ... */ after `end's. The name of the function or case will be set between the braces.
Hook run after verilog-mode updates AUTOs.
Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc. This will exclude signals referenced as pin connections in {...} or (...) from AUTOWIRE, AUTOOUTPUT and friends. See also AUTONOHOOKUP.
Non-nil means automatically indent line after newline.
Expand AUTOINOUT statements, as part of M-x verilog-auto. Make inout statements for any inout signal in an /*AUTOINST*/ that isn't declared elsewhere inside the module.
Limitations:
verilog-read-sub-decls).
If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.
If any concatenation, or bit-subscripts are missing in the AUTOINSTant's instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
Typedefs must match verilog-typedef-regexp, which is disabled by default.
Types are added to declarations if an AUTOLOGIC or
verilog-auto-wire-type is set to logic.
Signals matching verilog-auto-inout-ignore-regexp are not included.
An example (see verilog-auto-inst for what else is going on here):
module InstModule (inout io);
endmodule
module ExampInout (
/*AUTOINOUT*/
);
InstModule instName
(/*AUTOINST*/);
endmodule
Typing M-x verilog-auto will make this into:
module ExampInout (
/*AUTOINOUT*/
// Beginning of automatic inouts
inout io // To/From instName of InstModule.v
// End of automatics
);
InstModule instName
(/*AUTOINST*/
// Inouts
.io (io));
endmodule
You may also provide an optional regular expression, in which case only signals matching the regular expression will be included, or excluded if the regexp begins with ?! (question-mark exclamation-mark). For example the same expansion will result from only extracting inouts starting with i:
/*AUTOINOUT("^i")*/
Expand AUTOINOUTCOMP statements, as part of M-x verilog-auto.
Take input/output/inout statements from the specified module and
insert the inverse into the current module (inputs become outputs
and vice-versa.) This is useful for making test and stimulus
modules which need to have complementing I/O with another module.
Any I/O which are already defined in this module will not be
redefined. For the complement of this function, see
verilog-auto-inout-module.
Limitations:
Concatenation and outputting partial buses is not supported.
Module names must be resolvable to filenames. See verilog-auto-inst.
Signals are not inserted in the same order as in the original module, though they will appear to be in the same order to an AUTOINST instantiating either module.
An example:
module ExampMain
(input i,
output o,
inout io);
endmodule
module ExampBench (/*AUTOARG*/);
/*AUTOINOUTCOMP("ExampMain")*/
endmodule
Typing M-x verilog-auto will make this into:
module ExampShell (/*AUTOARG*/i, io, o);
/*AUTOINOUTCOMP("ExampMain")*/
// Beginning of automatic in/out/inouts
output i;
inout io;
input o;
// End of automatics
endmodule
You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting signals starting with i:
/*AUTOINOUTCOMP("ExampMain","^i")*/
You may also provide an optional third argument regular expression, in which case only signals which have that pin direction and data type matching that regular expression will be included. This matches against everything before the signal name in the declaration, for example against "input" (single bit), "output logic" (direction and type) or "output [1:0]" (direction and implicit type). You also probably want to skip spaces in your regexp.
For example, the below will result in matching the output "o" against the previous example's module:
/*AUTOINOUTCOMP("ExampMain","","^output.*")*/
You may also provide an optional fourth argument regular expression, which if not "" only signals which do NOT match that expression are included.
If non-nil, when creating AUTOINOUT, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.
Expand AUTOINOUTIN statements, as part of M-x verilog-auto.
Take input/output/inout statements from the specified module and
insert them as all inputs into the current module. This is
useful for making monitor modules which need to see all signals
as inputs based on another module. Any I/O which are already
defined in this module will not be redefined. See also
verilog-auto-inout-module.
Limitations:
Concatenation and outputting partial buses is not supported.
Module names must be resolvable to filenames. See verilog-auto-inst.
Signals are not inserted in the same order as in the original module, though they will appear to be in the same order to an AUTOINST instantiating either module.
An example:
module ExampMain
(input i,
output o,
inout io);
endmodule
module ExampInoutIn (/*AUTOARG*/);
/*AUTOINOUTIN("ExampMain")*/
endmodule
Typing M-x verilog-auto will make this into:
module ExampInoutIn (/*AUTOARG*/i, io, o);
/*AUTOINOUTIN("ExampMain")*/
// Beginning of automatic in/out/inouts
input i;
input io;
input o;
// End of automatics
endmodule
You may also provide an optional regular expression, in which case only signals matching the regular expression will be included, or excluded if the regexp begins with ?! (question-mark exclamation-mark). For example the same expansion will result from only extracting signals starting with i:
/*AUTOINOUTIN("ExampMain","^i")*/
Expand AUTOINOUTMODPORT statements, as part of M-x verilog-auto. Take input/output/inout statements from the specified interface and modport and insert into the current module. This is useful for making verification modules that connect to UVM interfaces.
The second parameter is a regexp of modports to read from in that interface.
The optional third parameter is a regular expression, and only signals matching the regular expression will be included.
The optional fourth parameter is a prefix to add to the signals.
Limitations:
Interface names must be resolvable to filenames. See verilog-auto-inst.
As with other autos, any inputs/outputs declared in the module will suppress the AUTO from redeclaring an inputs/outputs by the same name.
An example:
interface ExampIf
( input logic clk );
logic req_val;
logic [7:0] req_dat;
clocking mon_clkblk @(posedge clk);
input req_val;
input req_dat;
endclocking
modport mp(clocking mon_clkblk);
endinterface
module ExampMain
( input clk,
/*AUTOINOUTMODPORT("ExampIf", "mp")*/
);
ExampleIf i;
/*AUTOASSIGNMODPORT("ExampIf", "mp", "i")*/
endmodule
Typing M-x verilog-auto will make this into:
module ExampMain
( input clk,
/*AUTOINOUTMODPORT("ExampIf", "mp")*/
// Beginning of automatic in/out/inouts (from modport)
input req_val,
input [7:0] req_dat
// End of automatics
);
ExampleIf i;
/*AUTOASSIGNMODPORT("ExampIf", "mp", "i")*/
// Beginning of automatic assignments from modport
assign i.req_dat = req_dat;
assign i.req_val = req_val;
// End of automatics
endmodule
If the modport is part of a UVM monitor/driver class, this creates a wrapper module that may be used to instantiate the driver/monitor using AUTOINST in the testbench.
Expand AUTOINOUTMODULE statements, as part of M-x verilog-auto.
Take input/output/inout statements from the specified module and insert
into the current module. This is useful for making null templates and
shell modules which need to have identical I/O with another module.
Any I/O which are already defined in this module will not be redefined.
For the complement of this function, see verilog-auto-inout-comp,
and to make monitors with all inputs, see verilog-auto-inout-in.
Limitations:
Concatenation and outputting partial buses is not supported.
Module names must be resolvable to filenames. See verilog-auto-inst.
Signals are not inserted in the same order as in the original module, though they will appear to be in the same order to an AUTOINST instantiating either module.
Signals declared as "output reg" or "output wire" etc will lose the wire/reg declaration so that shell modules may generate those outputs differently. However, "output logic" is propagated.
An example:
module ExampMain
(input i,
output o,
inout io);
endmodule
module ExampShell (/*AUTOARG*/);
/*AUTOINOUTMODULE("ExampMain")*/
endmodule
Typing M-x verilog-auto will make this into:
module ExampShell (/*AUTOARG*/o, io, o);
/*AUTOINOUTMODULE("ExampMain")*/
// Beginning of automatic in/out/inouts
output o;
inout io;
input i;
// End of automatics
endmodule
You may also provide an optional regular expression, in which case only signals matching the regular expression will be included, or excluded if the regexp begins with ?! (question-mark exclamation-mark). For example the same expansion will result from only extracting signals starting with i:
/*AUTOINOUTMODULE("ExampMain","^i")*/
You may also provide an optional third argument regular expression, in which case only signals which have that pin direction and data type matching that regular expression will be included. This matches against everything before the signal name in the declaration, for example against "input" (single bit), "output logic" (direction and type) or "output [1:0]" (direction and implicit type). You also probably want to skip spaces in your regexp.
For example, the below will result in matching the output "o" against the previous example's module:
/*AUTOINOUTMODULE("ExampMain","","^output.*")*/
You may also provide an optional fourth argument regular expression, which if not "" only signals which do NOT match that expression are included.
Expand AUTOINOUTPARAM statements, as part of M-x verilog-auto.
Take input/output/inout statements from the specified module and insert
into the current module. This is useful for making null templates and
shell modules which need to have identical I/O with another module.
Any I/O which are already defined in this module will not be redefined.
For the complement of this function, see verilog-auto-inout-comp,
and to make monitors with all inputs, see verilog-auto-inout-in.
Limitations:
Module names must be resolvable to filenames. See verilog-auto-inst.
Parameters are inserted in the same order as in the original module.
Parameters do not have values, which is SystemVerilog 2009 syntax.
An example:
module ExampMain ();
parameter PARAM = 22;
endmodule
module ExampInoutParam ();
/*AUTOINOUTPARAM("ExampMain")*/
endmodule
Typing M-x verilog-auto will make this into:
module ExampInoutParam ();
/*AUTOINOUTPARAM("ExampMain")*/
// Beginning of automatic parameters (from specific module)
parameter PARAM;
// End of automatics
endmodule
You may also provide an optional regular expression, in which case only parameters matching the regular expression will be included. For example the same expansion will result from only extracting parameters starting with i:
/*AUTOINOUTPARAM("ExampMain","^i")*/
Expand AUTOINPUT statements, as part of M-x verilog-auto. Make input statements for any input signal into an /*AUTOINST*/ that isn't declared elsewhere inside the module. This is useful for modules which only instantiate other modules.
Limitations:
verilog-read-sub-decls).
If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.
If any concatenation, or bit-subscripts are missing in the AUTOINSTant's instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
Typedefs must match verilog-typedef-regexp, which is disabled by default.
Types are added to declarations if an AUTOLOGIC or
verilog-auto-wire-type is set to logic.
Signals matching verilog-auto-input-ignore-regexp are not included.
An example (see verilog-auto-inst for what else is going on here):
module InstModule (input i);
endmodule
module ExampInput (
/*AUTOINPUT*/
);
InstModule instName
(/*AUTOINST*/);
endmodule
Typing M-x verilog-auto will make this into:
module ExampInput (
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input i // To instName of InstModule.v
// End of automatics
);
InstModule instName
(/*AUTOINST*/
// Inputs
.i (i));
endmodule
You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. or excluded if the regexp begins with ?! (question-mark exclamation-mark). For example the same expansion will result from only extracting inputs starting with i:
/*AUTOINPUT("^i")*/
If non-nil, when creating AUTOINPUT, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.
Expand AUTOINSERTLAST statements, as part of M-x verilog-auto. The Lisp code provided is called after all other AUTOS have been expanded, and the Lisp code generally will call `insert' to insert text into the current file beginning on the line after the AUTOINSERTLAST.
Other than when called (after AUTOs are expanded), the functionality
is otherwise identical to AUTOINSERTLISP and verilog-auto-insert-lisp which
executes before (as opposed to after) other AUTOs.
See verilog-auto-insert-lisp for examples.
Expand AUTOINSERTLISP statements, as part of M-x verilog-auto. The Lisp code provided is called before other AUTOS are expanded, and the Lisp code generally will call `insert' to insert text into the current file beginning on the line after the AUTOINSERTLISP.
See also AUTOINSERTLAST and verilog-auto-insert-last which
executes after (as opposed to before) other AUTOs.
See also AUTO_LISP, which takes a Lisp expression and evaluates
it during verilog-auto-inst but does not insert any text.
An example:
module ExampInsertLisp;
/*AUTOINSERTLISP(my-verilog-insert-hello "world")*/
endmodule
// For this example we declare the function in the
// module's file itself. Often you'd define it instead
// in a site-start.el or init file.
/*
Local Variables:
eval:
(defun my-verilog-insert-hello (who)
(insert (concat "initial $write(\"hello " who "\");\n")))
End:
*/
Typing M-x verilog-auto will call my-verilog-insert-hello and expand the above into:
/*AUTOINSERTLISP(my-verilog-insert-hello "world")*/
// Beginning of automatic insert Lisp
initial $write("hello world");
// End of automatics
You can also call an external program and insert the returned text:
/*AUTOINSERTLISP(insert (shell-command-to-string "echo //hello"))*/
// Beginning of automatic insert lisp
//hello
// End of automatics
Expand AUTOINST statements, as part of M-x verilog-auto. Replace the pin connections to an instantiation or interface declaration with ones automatically derived from the module or interface header of the instantiated item.
You may also provide an optional regular expression, in which case only I/O matching the regular expression will be included, or excluded if the regexp begins with ?! (question-mark exclamation-mark).
If verilog-auto-star-expand is set, also expand SystemVerilog .* ports,
and delete them before saving unless verilog-auto-star-save is set.
See verilog-auto-star for more information.
The pins are printed in declaration order or alphabetically,
based on the verilog-auto-inst-sort variable.
To debug what file a submodule comes from, in a buffer with AUTOINST, use M-x verilog-goto-defun to switch buffers to the point containing the given symbol (i.e. a submodule name)'s module definition.
Limitations:
verilog-library-extensions, and being found in the same directory, or
by changing the variable verilog-library-flags or
verilog-library-directories. Macros `modname are translated through the
vh-{name} Emacs variable, if that is not found, it just ignores the `.
In templates you must have one signal per line, ending in a ), or ));, and have proper () nesting, including a final ); to end the template.
Typedefs must match verilog-typedef-regexp, which is disabled by default.
SystemVerilog multidimensional input/output has only experimental support.
SystemVerilog .name syntax is used if verilog-auto-inst-dot-name is set.
Parameters referenced by the instantiation will remain symbolic, unless
verilog-auto-inst-param-value is set.
Gate primitives (and/or) may have AUTOINST for the purpose of AUTOWIRE declarations, etc. Gates are the only case when position based connections are passed.
The array part of arrayed instances are ignored; this may result in undesirable default AUTOINST connections; use a template instead.
For example, first take the submodule InstModule.v:
module InstModule (o,i);
output [31:0] o;
input i;
wire [31:0] o = {32{i}};
endmodule
This is then used in an upper level module:
module ExampInst (o,i);
output o;
input i;
InstModule instName
(/*AUTOINST*/);
endmodule
Typing M-x verilog-auto will make this into:
module ExampInst (o,i);
output o;
input i;
InstModule instName
(/*AUTOINST*/
// Outputs
.o (o[31:0]),
// Inputs
.i (i));
endmodule
Where the list of inputs and outputs came from the inst module.
Exceptions:
When you need to violate this suggestion there are two ways to list exceptions, placing them before the AUTOINST, or using templates.
Any ports defined before the /*AUTOINST*/ are not included in the list of automatics. This is similar to making a template as described below, but is restricted to simple connections just like you normally make. Also note that any signals before the AUTOINST will only be picked up by AUTOWIRE if you have the appropriate // Input or // Output comment, and exactly the same line formatting as AUTOINST itself uses.
InstModule instName
(// Inputs
.i (my_i_dont_mess_with_it),
/*AUTOINST*/
// Outputs
.o (o[31:0]));
Templates:
/* InstModule AUTO_TEMPLATE (
.sig3 (sigz[]),
);
*/
verilog-mode simply searches up for the closest template.
Thus you can have multiple templates for the same module, just alternate
between the template for an instantiation and the instantiation itself.
(For backward compatibility if no template is found above, it
will also look below, but do not use this behavior in new designs.)
The module name must be the same as the name of the module in the instantiation name, and the code "AUTO_TEMPLATE" must be in these exact words and capitalized. Only signals that must be different for each instantiation need to be listed.
Inside a template, a [] in a connection name (with nothing else inside the brackets) will be replaced by the same bus subscript as it is being connected to, or the [] will be removed if it is a single bit signal.
Inside a template, a [][] in a connection name will behave similarly to a [] for scalar or single-dimensional connection; for a multidimensional connection it will print a comment similar to that printed when a template is not used. Generally it is a good idea to do this for all connections in a template, as then they will work for any width signal, and with AUTOWIRE. See PTL_BUS becoming PTL_BUSNEW below.
Inside a template, a [] in a connection name (with nothing else inside the brackets) will be replaced by the same bus subscript as it is being connected to, or the [] will be removed if it is a single bit signal. Generally it is a good idea to do this for all connections in a template, as then they will work for any width signal, and with AUTOWIRE. See PTL_BUS becoming PTL_BUSNEW below.
If you have a complicated template, set verilog-auto-inst-template-numbers
to see which regexps are matching. Don't leave that mode set after
debugging is completed though, it will result in lots of extra differences
and merge conflicts.
If a connection name does not match any template, it is
connected to a net by the same name as the port (unless
verilog-auto-inst-template-required is true).
Setting verilog-auto-template-warn-unused will report errors
if any template lines are unused.
For example:
/* InstModule AUTO_TEMPLATE (
.ptl_bus (ptl_busnew[]),
);
*/
InstModule ms2m (/*AUTOINST*/);
InstModule ms2m (/*AUTOINST*/
// Outputs
.NotInTemplate (NotInTemplate),
.ptl_bus (ptl_busnew[3:0]),
....
Multiple Module Templates:
/* InstModuleA AUTO_TEMPLATE
InstModuleB AUTO_TEMPLATE
InstModuleC AUTO_TEMPLATE
InstModuleD AUTO_TEMPLATE (
.ptl_bus (ptl_busnew[]),
);
*/
@ Templates:
/* InstName AUTO_TEMPLATE <optional "REGEXP"> (
.sig1 (sigx[@]),
.sig2 (sigy[@"(% (+ 1 @) 4)"]),
);
*/
If a regular expression is provided, the @ character will be replaced with the first () grouping that matches against the cell name. Using a regexp of `\([0-9]+\)' provides identical values for @ as when no regexp is provided. If you use multiple layers of parenthesis, `test\([^0-9]+\)_\([0-9]+\)' would replace @ with non-number characters after test and before _, whereas `\(test\([a-z]+\)_\([0-9]+\)\)' would replace @ with the entire match.
For example:
/* InstModule AUTO_TEMPLATE (
.ptl_mapvalidx (ptl_mapvalid[@]),
.ptl_mapvalidp1x (ptl_mapvalid[@"(% (+ 1 @) 4)"]),
);
*/
InstModule ms2m (/*AUTOINST*/);
InstModule ms2m (/*AUTOINST*/
// Outputs
.ptl_mapvalidx (ptl_mapvalid[2]),
.ptl_mapvalidp1x (ptl_mapvalid[3]));
Alternatively, using a regular expression for @:
/* InstModule AUTO_TEMPLATE "_\([a-z]+\)" (
.ptl_mapvalidx (@_ptl_mapvalid),
.ptl_mapvalidp1x (ptl_mapvalid_@),
);
*/
InstModule ms2_FOO (/*AUTOINST*/);
InstModule ms2_BAR (/*AUTOINST*/);
InstModule ms2_FOO (/*AUTOINST*/
// Outputs
.ptl_mapvalidx (FOO_ptl_mapvalid),
.ptl_mapvalidp1x (ptl_mapvalid_FOO));
InstModule ms2_BAR (/*AUTOINST*/
// Outputs
.ptl_mapvalidx (BAR_ptl_mapvalid),
.ptl_mapvalidp1x (ptl_mapvalid_BAR));
Regexp Templates:
.pci_req\([0-9]+\)_l (pci_req_jtag_[\1]),
Since \([0-9]+\) is so common and ugly to read, a @ in the port name does the same thing. (Note a @ in the connection/replacement text is completely different -- still use \1 there!) Thus this is the same as the above template:
.pci_req@_l (pci_req_jtag_[\1]),
.\(.*\)_l (\1_[]),
Lisp Templates:
If the syntax @"( ... )" is found in a connection, the expression in quotes will be evaluated as a Lisp expression, with @ replaced by the instantiation number. The MAPVALIDP1X example above would put @+1 modulo 4 into the brackets. Quote all double-quotes inside the expression with a leading backslash (\"...\"); or if the Lisp template is also a regexp template backslash the backslash quote (\\"...\\").
There are special variables defined that are useful in these Lisp functions:
vl-name Name portion of the input/output port.
vl-bits Bus bits portion of the input/output port (`[2:0]').
vl-mbits Multidimensional array bits for port (`[2:0][3:0]').
vl-width Width of the input/output port (`3' for [2:0]).
May be a (...) expression if bits isn't a constant.
vl-dir Direction of the pin input/output/inout/interface.
vl-memory The unpacked array part of the I/O port (`[5:0]').
vl-modport The modport, if an interface with a modport.
vl-cell-type Module name/type of the cell (`InstModule').
vl-cell-name Instance name of the cell (`instName').
verilog-read-defines which can set vh-{definename} variables for use
here. Also, any comments of the form:
/*AUTO_LISP(setq foo 1)*/
verilog-auto-insert-lisp if you want the output from your
lisp function to be inserted.)
Note that when using lisp expressions errors may occur when @ is not a number; you may need to use the standard Emacs Lisp functions `number-to-string' and `string-to-number'.
After the evaluation is completed, @ substitution and [] substitution occur.
Ignoring Hookup:
.pci_req_l (pci_req_not_to_wire), //AUTONOHOOKUP
For more information see the M-x verilog-faq and forums at URL `https://www.veripool.org'.
Indent-to column number for net name part of AUTOINST created pin.
Non-nil means when creating ports with AUTOINST, use .name syntax.
This will use ".port" instead of ".port(port)" when possible.
This is only legal in SystemVerilog files, and will confuse older
simulators. Setting verilog-auto-inst-vector to nil may also
be desirable to increase how often .name will be used.
Non-nil means include interfaced ports in AUTOINST expansions.
Expand AUTOINSTPARAM statements, as part of M-x verilog-auto. Replace the parameter connections to an instantiation with ones automatically derived from the module header of the instantiated netlist.
You may also provide an optional regular expression, in which case only parameters matching the regular expression will be included, or excluded if the regexp begins with ?! (question-mark exclamation-mark).
See M-x verilog-auto-inst for limitations, and templates to customize the output.
For example, first take the submodule InstModule.v:
module InstModule (o,i);
parameter PAR;
endmodule
This is then used in an upper level module:
module ExampInstParam (o,i);
parameter PAR;
InstModule #(/*AUTOINSTPARAM*/)
instName (/*AUTOINST*/);
endmodule
Typing M-x verilog-auto will make this into:
module ExampInstParam (o,i);
parameter PAR;
InstModule #(/*AUTOINSTPARAM*/
// Parameters
.PAR (PAR))
instName (/*AUTOINST*/);
endmodule
Where the list of parameter connections come from the inst module.
Templates:
Non-nil means AUTOINST will replace parameters with the parameter value. If nil, leave parameters as symbolic names.
Parameters must be in Verilog 2001 format #(...), and if a parameter is not listed as such there (as when the default value is acceptable), it will not be replaced, and will remain symbolic.
For example, imagine a submodule uses parameters to declare the size of its inputs. This is then used by an upper module:
module InstModule (o,i);
parameter WIDTH;
input [WIDTH-1:0] i;
parameter type OUT_t;
output OUT_t o;
endmodule
module ExampParamVal1;
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output OUT_t o;
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
.o (o),
.i (i[WIDTH-1:0]));
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
Note even though WIDTH=10, the AUTOINST has left the parameter as a symbolic name. Likewise the OUT_t is preserved as the name from the instantiated module.
If verilog-auto-inst-param-value is set, this will
instead expand to:
module ExampParamVal1;
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output upper_t o;
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
.o (o),
.i (i[9:0]));
Note that the instantiation now has "i[9:0]" as the WIDTH
was expanded. Likewise the data type of "o" in the AUTOOUTPUT
is now upper_t, from the OUT_t parameter override.
This second expansion of parameter types can be overridden with
verilog-auto-inst-param-value-type.
Non-nil means expand parameter type in instantiations. If nil, leave parameter types as symbolic names.
See verilog-auto-inst-param-value.
Non-nil means AUTOINST signals will be sorted, not in declaration order. Also affects AUTOINSTPARAM. Declaration order is the default for backward compatibility, and as some teams prefer signals that are declared together to remain together. Sorted order reduces changes when declarations are moved around in a file. Sorting is within input/output/inout groupings, there is intentionally no option to intermix between input/output/inouts.
See also verilog-auto-arg-sort.
If true, when creating templated ports with AUTOINST, add a comment.
If t, the comment will add the line number of the template that was used for that port declaration. This setting is suggested only for debugging use, as regular use may cause a large numbers of merge conflicts.
If `lhs', the comment will show the left hand side of the AUTO_TEMPLATE rule that is matched. This is less precise than numbering (t) when multiple rules have the same pin name, but won't merge conflict.
If non-nil, when creating a port with AUTOINST, require a template. Any port which does not have a template will be omitted from the instantiation.
If nil, if a port is not templated it will be inserted to connect to a net with the same name as the port.
Non-nil means when creating default ports with AUTOINST, use bus subscripts. If nil, skip the subscript when it matches the entire bus as declared in the module (AUTOWIRE signals always are subscripted, you must manually declare the wire to have the subscripts removed.) Setting this to nil may speed up some simulators, but is less general and harder to read, so avoid. If `unsigned', use vectors for unsigned types (like using true, otherwise no vectors if sizes match (like using nil).
Type of statements to lineup across multiple lines. If `all' is selected, then all line ups described below are done.
If `declarations', then just declarations are lined up with any preceding declarations, taking into account widths and the like, so or example the code:
reg [31:0] a;
reg b;
would become
reg [31:0] a;
reg b;
If `assignment', then assignments are lined up with any preceding assignments, so for example the code
a_long_variable <= b + c;
d = e + f;
would become
a_long_variable <= b + c;
d = e + f;
In order to speed up editing, large blocks of statements are lined up only when a M-x verilog-pretty-expr is typed; and large blocks of declarations are lineup only when M-x verilog-pretty-declarations is typed.
Expand AUTOLOGIC statements, as part of M-x verilog-auto. Make wire statements using the SystemVerilog logic keyword. This is currently equivalent to:
/*AUTOWIRE*/
with the below at the bottom of the file
// Local Variables:
// verilog-auto-wire-type:"logic"
// End:
In the future AUTOLOGIC may declare additional identifiers, while AUTOWIRE will not.
Non-nil means automatically newline after semicolons.
Expand AUTOOUTPUT statements, as part of M-x verilog-auto. Make output statements for any output signal from an /*AUTOINST*/ that isn't an input to another AUTOINST. This is useful for modules which only instantiate other modules.
Limitations:
verilog-read-sub-decls).
If placed inside the parenthesis of a module declaration, it creates Verilog 2001 style, else uses Verilog 1995 style.
If any concatenation, or bit-subscripts are missing in the AUTOINSTant's instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
Typedefs must match verilog-typedef-regexp, which is disabled by default.
Types are added to declarations if an AUTOLOGIC or
verilog-auto-wire-type is set to logic.
Signals matching verilog-auto-output-ignore-regexp are not included.
An example (see verilog-auto-inst for what else is going on here):
module InstModule (output o);
endmodule
module ExampOutput
(/*AUTOOUTPUT*/
);
InstModule instName
(/*AUTOINST*/);
endmodule
Typing M-x verilog-auto will make this into:
module ExampOutput
(/*AUTOOUTPUT*/
// Beginning of automatic outputs
output o // From instName of InstModule.v
// End of automatics
);
InstModule instName
(/*AUTOINST*/
// Outputs
.o (o));
endmodule
You may also provide an optional regular expression, in which case only signals matching the regular expression will be included. For example the same expansion will result from only extracting outputs starting with ov:
/*AUTOOUTPUT("^ov")*/
Expand AUTOOUTPUTEVERY statements, as part of M-x verilog-auto. Make output statements for any signals that aren't primary inputs or outputs already. This makes every signal in the design an output. This is useful to get synthesis to preserve every signal in the design, since it won't optimize away the outputs.
An example:
module ExampOutputEvery (o,i,tempa,tempb);
output o;
input i;
/*AUTOOUTPUTEVERY*/
wire tempa = i;
wire tempb = tempa;
wire o = tempb;
endmodule
Typing M-x verilog-auto will make this into:
module ExampOutputEvery (
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output o,
output tempa,
output tempb,
// End of automatics
input i
);
wire tempa = i;
wire tempb = tempa;
wire o = tempb;
endmodule
You may also provide an optional regular expression, in which case only signals matching the regular expression will be included,or excluded if the regexp begins with ?! (question-mark exclamation-mark). For example the same expansion will result from only extracting outputs starting with ov:
/*AUTOOUTPUTEVERY("^ov")*/
If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.
Non-nil means to automatically read includes before AUTOs.
This will do a verilog-read-defines and verilog-read-includes before
each AUTO expansion. This makes it easier to embed defines and includes,
but can result in very slow reading times if there are many or large
include files.
Expand AUTOREG statements, as part of M-x verilog-auto.
Make reg statements for any output that isn't already declared,
and isn't a wire output from a block. verilog-auto-wire-type
may be used to change the datatype of the declarations.
Limitations:
verilog-read-sub-decls).
This does NOT work on memories, declare those yourself.
An example:
module ExampReg (o,i);
output o;
input i;
/*AUTOREG*/
always o = i;
endmodule
Typing M-x verilog-auto will make this into:
module ExampReg (o,i);
output o;
input i;
/*AUTOREG*/
// Beginning of automatic regs
reg o;
// End of automatics
always o = i;
endmodule
Expand AUTOREGINPUT statements, as part of M-x verilog-auto. Make reg statements instantiation inputs that aren't already declared or assigned to. This is useful for making a top level shell for testing the module that is to be instantiated.
Limitations:
verilog-read-sub-decls).
This does NOT work on memories, declare those yourself.
Assignments cause the assigned-to variable not to be declared unless
the name matches verilog-auto-reg-input-assigned-ignore-regexp.
An example (see verilog-auto-inst for what else is going on here):
module InstModule (input i);
endmodule
module ExampRegInput ();
/*AUTOREGINPUT*/
InstModule instName
(/*AUTOINST*/);
endmodule
Typing M-x verilog-auto will make this into:
module ExampRegInput ();
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs
reg i; // To instName of InstModule.v
// End of automatics
InstModule instName
(/*AUTOINST*/
// Inputs
.i (i));
endmodule
If non-nil, when creating AUTOINPUTREG, ignore signals matching this regexp.
Expand AUTORESET statements, as part of M-x verilog-auto. Replace the /*AUTORESET*/ comment with code to initialize all registers set elsewhere in the always block.
Limitations:
AUTORESET uses <= if the signal has a <= assignment in the block, else it uses =.
If <= is used, all = assigned variables are ignored if
verilog-auto-reset-blocking-in-non is nil; they are presumed
to be temporaries.
/*AUTORESET*/ presumes that any signals mentioned between the previous begin/case/if statement and the AUTORESET comment are being reset manually and should not be automatically reset. This includes omitting any signals used on the right hand side of assignments.
By default, AUTORESET will include the width of the signal in the
autos, SystemVerilog designs may want to change this. To control
this behavior, see verilog-auto-reset-widths. In some cases
AUTORESET must use a \='0 assignment and it will print NOWIDTH; use
verilog-auto-reset-widths unbased to prevent this.
AUTORESET ties signals to deasserted, which is presumed to be zero.
Signals that match verilog-active-low-regexp will be deasserted by tying
them to a one.
AUTORESET may try to reset arrays or structures that cannot be reset by a simple assignment, resulting in compile errors. This is a feature to be taken as a hint that you need to reset these signals manually (or put them into a "`ifdef NEVER signal<=\='0; `endif" so Verilog-Mode ignores them.)
An example:
module ExampReset ();
always @(posedge clk or negedge reset_l) begin
if (!reset_l) begin
c <= 1;
/*AUTORESET*/
end
else begin
a <= in_a;
b <= in_b;
c <= in_c;
end
end
endmodule
Typing M-x verilog-auto will make this into:
...
c <= 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a <= 1'h0;
b <= 1'h0;
// End of automatics
...
Non-nil means AUTORESET will reset blocking statements. When true, AUTORESET will reset in blocking statements those signals which were assigned with blocking assignments (=) even in a block with non-blocking assignments (<=).
If nil, all blocking assigned signals are ignored when any
non-blocking assignment is in the AUTORESET block. This allows
blocking assignments to be used for temporary values and not have
those temporaries reset. See example in verilog-auto-reset.
Non-nil means AUTORESET should determine the width of signals. This is then used to set the width of the zero (32'h0 for example). This is required by some lint tools that aren't smart enough to ignore widths of the constant zero. This may result in ugly code when parameters determine the MSB or LSB of a signal inside an AUTORESET.
If nil, AUTORESET uses "0" as the constant.
If `unbased', AUTORESET used the unbased unsized literal "\='0" as the constant. This setting is strongly recommended for SystemVerilog designs.
Update automatics with M-x verilog-auto, save the buffer, and compile.
Non-nil indicates action to take when saving a Verilog buffer with AUTOs. A value of `force' will always do a M-x verilog-auto automatically if needed on every save. A value of `detect' will do M-x verilog-auto automatically when it thinks necessary. A value of `ask' will query the user when it thinks updating is needed.
You should not rely on the `ask' or `detect' policies, they are safeguards only. They do not detect when AUTOINSTs need to be updated because a sub-module's port list has changed.
Expand AUTOSENSE statements, as part of M-x verilog-auto.
Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
with one automatically derived from all inputs declared in the always
statement. Signals that are generated within the same always block are NOT
placed into the sensitivity list (see verilog-auto-sense-include-inputs).
Long lines are split based on the `fill-column', see M-x set-fill-column.
Limitations:
Constant signals:
/* AUTO_CONSTANT( `this_is_really_constant_dont_autosense_it ) */
OOps!
An example:
always @ (/*AS*/) begin
/*AUTO_CONSTANT(`constant) */
outin = ina | inb | `constant;
out = outin;
end
Typing M-x verilog-auto will make this into:
always @ (/*AS*/ina or inb) begin
/*AUTO_CONSTANT(`constant) */
outin = ina | inb | `constant;
out = outin;
end
Note in Verilog 2001, you can often get the same result from the new @* operator. (This was added to the language in part due to AUTOSENSE!)
always @* begin
outin = ina | inb | `constant;
out = outin;
end
Non-nil means AUTOSENSE should assume all defines represent constants. When true, the defines will not be included in sensitivity lists. To maintain compatibility with other sites, this should be set at the bottom of each Verilog file that requires it, rather than being set globally.
Non-nil means AUTOSENSE should include all inputs. If nil, only inputs that are NOT output signals in the same block are included.
Non-nil means AUTOs will simplify expressions when calculating bit ranges. When nil, do not simply ranges, which may simplify the output, but may cause problems when there are multiple instantiations outputting to the same wire. To maintain compatibility with other sites, this should be set at the bottom of each Verilog file that requires it, rather than being set globally.
Expand SystemVerilog .* pins, as part of M-x verilog-auto.
If verilog-auto-star-expand is set, .* pins are treated if they were
AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
will also ignore any .* that are not last in your pin list (this prevents
it from deleting pins following the .* when it expands the AUTOINST.)
On writing your file, unless verilog-auto-star-save is set, any
non-templated expanded pins will be removed. You may do this at any time
with M-x verilog-delete-auto-star-implicit.
If you are converting a module to use .* for the first time, you may wish to use M-x verilog-inject-auto and then replace the created AUTOINST with .*.
See verilog-auto-inst for examples, templates, and more information.
Non-nil means to expand SystemVerilog .* instance ports.
They will be expanded in the same way as if there was an AUTOINST in the
instantiation. See also verilog-auto-star and verilog-auto-star-save.
Non-nil means save to disk SystemVerilog .* instance expansions.
A nil value indicates direct connections will be removed before saving.
Only meaningful to those created due to verilog-auto-star-expand being set.
Instead of setting this, you may want to use /*AUTOINST*/, which will always be saved.
Non-nil means report warning if an AUTO_TEMPLATE line is not used. This feature is not supported before Emacs 21.1 or XEmacs 21.4.
Expand AUTOTIEOFF statements, as part of M-x verilog-auto. Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output signals to deasserted.
/*AUTOTIEOFF*/ is used to make stub modules; modules that have the same input/output list as another module, but no internals. Specifically, it finds all outputs in the module, and if that input is not otherwise declared as a register or wire, nor comes from a AUTOINST submodule's output, creates a tieoff. AUTOTIEOFF does not examine assignments to determine what is already driven.
AUTORESET ties signals to deasserted, which is presumed to be zero.
Signals that match verilog-active-low-regexp will be deasserted by tying
them to a one.
You can add signals you do not want included in AUTOTIEOFF with
verilog-auto-tieoff-ignore-regexp.
verilog-auto-wire-type may be used to change the datatype of
the declarations.
verilog-auto-reset-widths may be used to change how the tieoff
value's width is generated.
An example of making a stub for another module:
module ExampMain
#(parameter P)
(input i, output o, inout io);
endmodule
module ExampStub (/*AUTOARG*/);
/*AUTOINOUTPARAM("ExampMain")*/
/*AUTOINOUTMODULE("ExampMain")*/
/*AUTOTIEOFF*/
// verilator lint_off UNUSED
wire _unused_ok = &{1\='b0,
/*AUTOUNUSED*/
1\='b0};
// verilator lint_on UNUSED
endmodule
Typing M-x verilog-auto will make this into:
...
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs
wire [2:0] o = 3\='b0;
// End of automatics
...
Data type used for the declaration for AUTOTIEOFF. If "wire" then create a wire, if "assign" create an assignment, else the data type for variable creation.
If non-nil, when creating AUTOTIEOFF, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.
Expand AUTOUNDEF statements, as part of M-x verilog-auto. Take any `defines since the last AUTOUNDEF in the current file and create `undefs for them. This is used to insure that file-local defines do not pollute the global `define name space.
Limitations:
AUTOUNDEF suppresses creating an `undef for any define that was `undefed before the AUTOUNDEF. This may be used to work around the ignoring of `ifdefs as shown below.
An example:
`define XX_FOO
`define M_BAR(x)
`define M_BAZ
...
`ifdef NEVER
`undef M_BAZ // Emacs will see this and not `undef M_BAZ
`endif
...
/*AUTOUNDEF*/
Typing M-x verilog-auto will make this into:
...
/*AUTOUNDEF*/
// Beginning of automatic undefs
`undef M_BAR
`undef XX_FOO
// End of automatics
You may also provide an optional regular expression, in which case only defines the regular expression will be undefed.
Expand AUTOUNUSED statements, as part of M-x verilog-auto. Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused input and inout signals.
/*AUTOUNUSED*/ is used to make stub modules; modules that have the same input/output list as another module, but no internals. Specifically, it finds all inputs and inouts in the module, and if that input is not otherwise used, adds it to a comma separated list.
The comma separated list is intended to be used to create a _unused_ok signal. Using the exact name "_unused_ok" for name of the temporary signal is recommended as it will insure maximum forward compatibility, it also makes lint warnings easy to understand; ignore any unused warnings with "unused" in the signal name.
To reduce simulation time, the _unused_ok signal should be forced to a constant to prevent wiggling. The easiest thing to do is use a reduction-and with 1\='b0 as shown.
This way all unused signals are in one place, making it convenient to add your tool's specific pragmas around the assignment to disable any unused warnings.
You can add signals you do not want included in AUTOUNUSED with
verilog-auto-unused-ignore-regexp.
An example of making a stub for another module:
module ExampMain
(input unused_input_a, input unused_input_b);
endmodule
module ExampStub2 (/*AUTOARG*/);
/*AUTOINOUTPARAM("ExampMain")*/
/*AUTOINOUTMODULE("ExampMain")*/
/*AUTOTIEOFF*/
// verilator lint_off UNUSED
wire _unused_ok = &{1\='b0,
/*AUTOUNUSED*/
1\='b0};
// verilator lint_on UNUSED
endmodule
Typing M-x verilog-auto will make this into:
...
// verilator lint_off UNUSED
wire _unused_ok = &{1\='b0,
/*AUTOUNUSED*/
// Beginning of automatics
unused_input_a,
unused_input_b
// End of automatics
1\='b0};
// verilator lint_on UNUSED
endmodule
If non-nil, when creating AUTOUNUSED, ignore signals matching this regexp. See the M-x verilog-faq for examples on using this.
Expand AUTOWIRE statements, as part of M-x verilog-auto.
Make wire statements for instantiations outputs that aren't
already declared. verilog-auto-wire-type may be used to change
the datatype of the declarations.
Limitations:
verilog-read-sub-decls),
and all buses must have widths, such as those from AUTOINST, or using []
in AUTO_TEMPLATEs.
This does NOT work on memories or SystemVerilog .name connections, declare those yourself.
Verilog mode will add "Couldn't Merge" comments to signals it cannot determine how to bus together. This occurs when you have ports with non-numeric or non-sequential bus subscripts. If Verilog mode mis-guessed, you'll have to declare them yourself.
An example (see verilog-auto-inst for what else is going on here):
module ExampWire (i);
input i;
/*AUTOWIRE*/
InstModule instName
(/*AUTOINST*/);
endmodule
Typing M-x verilog-auto will make this into:
module ExampWire (i);
input i;
/*AUTOWIRE*/
// Beginning of automatic wires
wire [31:0] o; // From instName of InstModule.v
// End of automatics
InstModule instName
(/*AUTOINST*/
// Outputs
.o (o[31:0]),
// Inputs
.i (i));
wire o = | ov;
endmodule
Non-nil indicates to insert to/from comments with verilog-auto-wire etc.
Non-nil specifies the data type to use with verilog-auto-wire etc.
Set this to "logic" for SystemVerilog code, or use verilog-auto-logic.
Set this to "wire" to force use of wire when logic is otherwise appropriate;
this is generally only appropriate when making a non-SystemVerilog wrapper
containing SystemVerilog cells.
For use with --batch, perform automatic differences as a stand-alone tool. This sets up the appropriate Verilog mode environment, expand automatics with M-x verilog-diff-auto on all command-line files, and reports an error if any differences are observed. This is appropriate for adding to regressions to insure automatics are always properly maintained.
Hook run before verilog-mode updates AUTOs.
Hook run before verilog-mode deletes AUTOs.
Hook run before verilog-getopt-flags determines the Verilog option lists.
Hook run before verilog-save-font-no-change-functions removes highlighting.
Non-nil means verilog-mode regexps should ignore case.
This variable is t for backward compatibility; nil is suggested.
Indentation for case statements.
Indentation of Verilog statements split across lines.
Program and arguments to use to compile Verilog source.
Depending on the verilog-set-compile-command, this may be invoked when
you type M-x compile. When the compile completes, M-x next-error will take
you to the next lint error.
Program and arguments to use to annotate for coverage Verilog source.
Depending on the verilog-set-compile-command, this may be invoked when
you type M-x compile. When the compile completes, M-x next-error will take
you to the next lint error.
Convert verilog-library-flags and similar variables to command line.
Used for __FLAGS__ in verilog-expand-command.
Delete the automatic outputs, regs, and wires created by M-x verilog-auto. Use M-x verilog-auto to re-insert the updated AUTOs.
The hooks verilog-before-delete-auto-hook and verilog-delete-auto-hook are
called before and after this function, respectively.
Hook run after verilog-mode deletes AUTOs.
Delete all .* implicit connections created by verilog-auto-star.
This function will be called automatically at save unless
verilog-auto-star-save is set, any non-templated expanded pins will be
removed.
Expand AUTOs in a temporary buffer and indicate any change. Whitespace is ignored when detecting differences, but once a difference is detected, whitespace differences may be shown.
To call this from the command line, see M-x verilog-batch-diff-auto.
The action on differences is selected with
verilog-diff-function. The default is verilog-diff-report
which will report an error and run `ediff' in interactive mode,
or `diff' in batch mode.
Function to run when verilog-diff-auto detects differences.
Function takes three arguments, the original buffer, the
difference buffer, and the point in original buffer with the
first difference.
Report differences detected with verilog-diff-auto.
Differences are between buffers B1 and B2, starting at point
DIFFPT. This function is called via verilog-diff-function.
Replace meta-information in COMMAND and return it.
Where __FLAGS__ appears in the string verilog-current-flags
will be substituted. Where __FILE__ appears in the string, the
current buffer's file-name, without the directory portion, will
be substituted.
Tell the user their current version, and where to get the FAQ etc.
Font to use for Verilog Grouping Keywords (such as begin..end).
Font to use for translated off regions.
Non-nil means fontify declaration variables.
Convert verilog-library-flags into standard library variables.
Hook run after verilog-getopt-flags determines the Verilog option lists.
Move to specified Verilog module/interface/task/function.
The default is a name found in the buffer around point.
If search fails, other files are checked based on
verilog-library-flags.
Non-nil means highlight grouping keywords more dramatically.
If false, these words are in the `font-lock-type-face'; if True
then they are in verilog-font-lock-grouping-keywords-face.
Some find that special highlighting on these grouping constructs
allow the structure of the code to be understood at a glance.
Non-nil means highlight module statements for verilog-load-file-at-point.
When true, mousing over include file names will allow jumping to the
file referenced. If false, this is not supported.
Maximum size of declaration statement that undergoes highlighting.
Highlighting is performed only on the first verilog-highlight-max-lookahead
characters in a declaration statement.
Setting this variable to zero would remove this limit. Note that removing
the limit can greatly slow down highlighting for very large files.
Non-nil means highlight module statements for verilog-load-file-at-point.
When true, mousing over module names will allow jumping to the
module definition. If false, this is not supported. Setting
this is experimental, and may lead to bad performance.
Obsolete. Was non-nil means highlight SystemVerilog IEEE-1800 differently. All code is now highlighted as if SystemVerilog IEEE-1800.
Non-nil means background-highlight code excluded from translation.
That is, all code between "// synopsys translate_off" and
"// synopsys translate_on" is highlighted using a different background color
(face verilog-font-lock-translate-off-face).
Note: This will slow down on-the-fly fontification (and thus editing).
Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu entry "Fontify Buffer"). XEmacs: turn off and on font locking.
Non-nil means indent begin statements following if, else, while, etc. Otherwise, line them up.
Non-nil means indent classes inside packages. Otherwise, classes have zero indentation.
How to treat macro expansions in a declaration. If nil, indent as:
input [31:0] a;
input `CP;
output c;
If non-nil, treat as:
input [31:0] a;
input `CP ;
output c;
Non-nil means ignore indentation on lines that are part of a multiline define.
Regexp that matches lines that should be ignored for indentation.
Indentation of Verilog statements with respect to containing block.
Absolute indentation of first begin in a task or function block. Set to 0 to get such code to start at the left side of the screen.
Indentation of declarations with respect to containing block. Set to 0 to get them list right under containing block.
Indentation to add to each level of `ifdef declarations. Set to 0 to have all directives start at the left side of the screen.
Indentation of Module level Verilog statements (eg always, initial). Set to 0 to get initial and always statements lined up on the left side of your screen.
How to treat indenting items in a list. If t (the default), indent as:
always @( posedge a or
reset ) begin
If nil, treat as:
always @( posedge a or
reset ) begin
Examine legacy non-AUTO code and insert AUTOs in appropriate places.
Any always @ blocks with sensitivity lists that match computed lists will be replaced with /*AS*/ comments.
Any cells will get /*AUTOINST*/ added to the end of the pin list. Pins with have identical names will be deleted.
Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to support adding new ports. You may wish to delete older ports yourself.
For example:
module ExampInject (i, o);
input i;
input j;
output o;
always @ (i or j)
o = i | j;
InstModule instName
(.foobar(baz),
.j(j));
endmodule
Typing M-x verilog-inject-auto (with an appropriate submodule not shown) will make this into:
module ExampInject (i, o/*AUTOARG*/
// Inputs
j);
input i;
output o;
always @ (/*AS*/i or j)
o = i | j;
InstModule instName
(.foobar(baz),
/*AUTOINST*/
// Outputs
j(j));
endmodule
List of directories when looking for files for /*AUTOINST*/. The directory may be relative to the current file, or absolute. Environment variables are also expanded in the directory names. Having at least the current directory is a good idea.
You might want these defined in each file; put at the *END* of your file something like:
// Local Variables:
// verilog-library-directories:("." "subdir" "subdir2")
// End:
Verilog-mode attempts to detect changes to this local variable, but they are only insured to be correct when the file is first visited. Thus if you have problems, use M-x find-alternate-file RET to have these take effect.
See also verilog-library-flags, verilog-library-files
and verilog-library-extensions.
List of extensions to use when looking for files for /*AUTOINST*/.
See also verilog-library-flags, verilog-library-directories.
List of files to search for modules. AUTOINST will use this when it needs to resolve a module name. This is a complete path, usually to a technology file with many standard cells defined in it.
You might want these defined in each file; put at the *END* of your file something like:
// Local Variables:
// verilog-library-files:("/path/technology.v" "/path2/tech2.v")
// End:
Verilog-mode attempts to detect changes to this local variable, but they are only insured to be correct when the file is first visited. Thus if you have problems, use M-x find-alternate-file RET to have these take effect.
See also verilog-library-flags, verilog-library-directories.
List of standard Verilog arguments to use for /*AUTOINST*/.
These arguments are used to find files for verilog-auto, and match
the flags accepted by a standard Verilog-XL simulator.
-f filename Reads absolute verilog-library-flags from the filename.
-F filename Reads relative verilog-library-flags from the filename.
+incdir+dir Adds the directory to verilog-library-directories.
-Idir Adds the directory to verilog-library-directories.
-y dir Adds the directory to verilog-library-directories.
+libext+.v Adds the extensions to verilog-library-extensions.
-v filename Adds the filename to verilog-library-files.
filename Adds the filename to verilog-library-files.
This is not recommended, -v is a better choice.
You might want these defined in each file; put at the *END* of your file something like:
// Local Variables:
// verilog-library-flags:("-y dir -y otherdir")
// End:
Verilog-mode attempts to detect changes to this local variable, but they are only insured to be correct when the file is first visited. Thus if you have problems, use M-x find-alternate-file RET to have these take effect.
See also the variables mentioned above.
Unix program and arguments to call to run a lint checker on Verilog source.
Depending on the verilog-set-compile-command, this may be invoked when
you type M-x compile. When the compile completes, M-x next-error will take
you to the next lint error.
Load file under point.
If WARN, throw warning if not found.
Files are checked based on verilog-library-flags.
Minimum distance (in lines) between begin and end required before a comment. Setting this variable to zero results in every end acquiring a comment; the default avoids too many redundant comments in tight quarters.
Hook run after Verilog mode is loaded.
Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
Takes optional COMMAND or defaults to verilog-preprocessor, and
FILENAME to find directory to run in, or defaults to `buffer-file-name'.
Program and arguments to use to preprocess Verilog source.
This is invoked with verilog-preprocess, and depending on the
verilog-set-compile-command, may also be invoked when you type
M-x compile. When the compile completes, M-x next-error will
take you to the next lint error.
Line up declarations around point. Be verbose about progress unless optional QUIET set.
Line up expressions around point. If QUIET is non-nil, do not print messages showing the progress of line-up.
Read `defines and parameters for the current file, or optional FILENAME.
If the filename is provided, verilog-library-flags will be used to
resolve it. If optional RECURSE is non-nil, recurse through `includes.
Localparams must be simple assignments to constants, or have their own "localparam" label rather than a list of localparams. Thus:
localparam X = 5, Y = 10; // Ok
localparam X = {1\='b1, 2\='h2}; // Ok
localparam X = {1\='b1, 2\='h2}, Y = 10; // Bad, make into 2 localparam lines
Defines must be simple text substitutions, one on a line, starting at the beginning of the line. Any ifdefs or multiline comments around the define are ignored.
Defines are stored inside Emacs variables using the name vh-{definename}.
Localparams define what symbols are constants so that AUTOSENSE will not include them in sensitivity lists. However any parameters in the include file are not considered ports in the including file, thus will not appear in AUTOINSTPARAM lists for a parent module..
The file variables feature can be used to set defines that
verilog-mode can see; put at the *END* of your file something
like:
// Local Variables:
// vh-macro:"macro_definition"
// End:
If macros are defined earlier in the same file and you want their values, you can read them automatically with:
// Local Variables:
// verilog-auto-read-includes:t
// End:
Or a more specific alternative example, which requires having `enable-local-eval' non-nil:
// Local Variables:
// eval:(verilog-read-defines)
// eval:(verilog-read-defines "group_standard_includes.v")
// End:
Note these are only read when the file is first visited, you must use M-x find-alternate-file RET to have these take effect after editing them!
If you want to disable the "Process `eval' or hook local variables" warning message, you need to add to your init file:
(setq enable-local-eval t)
Read `includes for the current file.
This will find all of the `includes which are at the beginning of lines,
ignoring any ifdefs or multiline comments around them.
verilog-read-defines is then performed on the current and each included
file.
It is often useful put at the *END* of your file something like:
// Local Variables:
// verilog-auto-read-includes:t
// End:
Or the equivalent longer version, which requires having `enable-local-eval' non-nil:
// Local Variables:
// eval:(verilog-read-defines)
// eval:(verilog-read-includes)
// End:
Note includes are only read when the file is first visited, you must use M-x find-alternate-file RET to have these take effect after editing them!
It is good to get in the habit of including all needed files in each .v file that needs it, rather than waiting for compile time. This will aid this process, Verilint, and readability. To prevent defining the same variable over and over when many modules are compiled together, put a test around the inside each include file:
foo.v (an include file):
`ifndef _FOO_V // include if not already included
`define _FOO_V
... contents of file
`endif // _FOO_V
Internally parse signals going to modules under this module. Return an array of [ outputs inouts inputs ] signals for modules that are instantiated in this module. For example if declare A A (.B(SIG)) and SIG is an output, then SIG will be included in the list.
This only works on instantiations created with /*AUTOINST*/ converted by M-x verilog-auto-inst. Otherwise, it would have to read in the whole component library to determine connectivity of the design.
One work around for this problem is to manually create // Inputs and // Outputs comments above subcell signals, then have an empty AUTOINST, for example:
submod SubModuleName (
// Outputs
.out (out),
// Inputs
.in (in)
/*AUTOINST*/);
Execute BODY forms, saving state around insignificant change. Changes in text properties like `face' or `syntax-table' are considered insignificant. This macro allows text properties to be changed, even in a read-only buffer.
A change is considered significant if it affects the buffer text
in any way that isn't completely restored again. Any
user-visible changes to the buffer must not be within a
verilog-save-buffer-state.
Execute BODY forms, disabling all change hooks in BODY.
Includes temporary disabling of `font-lock' to restore the buffer
to full text form for parsing. Additional actions may be specified with
verilog-before-save-font-hook and verilog-after-save-font-hook.
For insignificant changes, see instead verilog-save-buffer-state.
Function to compute shell command to compile Verilog.
This reads verilog-tool and sets `compile-command'. This specifies the
program that executes when you type M-x compile or
M-x verilog-auto-save-compile.
By default verilog-tool uses a Makefile if one exists in the
current directory. If not, it is set to the verilog-linter,
verilog-compiler, verilog-coverage, verilog-preprocessor,
or verilog-simulator variables, as selected with the Verilog ->
"Choose Compilation Action" menu.
You should set verilog-tool or the other variables to the path and
arguments for your Verilog simulator. For example:
"vcs -p123 -O"
or a string like:
"(cd /tmp; surecov %s)".
In the former case, the path to the current buffer is concat'ed to the
value of verilog-tool; in the later, the path to the current buffer is
substituted for the %s.
Where __FLAGS__ appears in the string verilog-current-flags
will be substituted.
Where __FILE__ appears in the string, the variable `buffer-file-name' of the current buffer, without the directory portion, will be substituted.
Program and arguments to use to interpret Verilog source.
Depending on the verilog-set-compile-command, this may be invoked when
you type M-x compile. When the compile completes, M-x next-error will take
you to the next lint error.
Non-nil means TAB should always re-indent the current line. A nil value means TAB will only reindent when at the beginning of the line.
Non-nil means TAB moves to the right hand column in preparation for a comment.
Which tool to use for building compiler-command.
Either nil, verilog-linter, verilog-compiler,
verilog-coverage, verilog-preprocessor, or verilog-simulator.
Alternatively use the "Choose Compilation Action" menu. See
verilog-set-compile-command for more information.
If non-nil, regular expression that matches Verilog-2001 typedef names.
For example, "_t$" matches typedefs named with _t, as in the C language.
See also verilog-case-fold.
Print a warning with `format' using STRING and optional ARGS.
Call `error' using STRING and optional ARGS.
If verilog-warn-fatal is non-nil, call verilog-warn instead.
Non-nil means verilog-warn-error warnings are fatal `error's.